We have some signal integrity troubles with clock and data signals when programming our MSP430F5341 using Spy Bi-Wire (2 Wire JTAG)
We are using MSP-FET430UIF and connecting as described here http://processors.wiki.ti.com/index.php/JTAG_%28MSP430%29
On different type of products with different layouts we always seem to have this glitch on the SBW CLK line.
The programming works but the data and clock signal integrity suggests its just luck. This can't be expected behavior, any suggestions on what the culprit might be?