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MSP430F5341 Spy Bi-Wire signal integrity issue

Other Parts Discussed in Thread: MSP430F5341

Hello,

We have some signal integrity troubles with clock and data signals when programming our MSP430F5341 using Spy Bi-Wire (2 Wire JTAG)


We are using MSP-FET430UIF and connecting as described here http://processors.wiki.ti.com/index.php/JTAG_%28MSP430%29

On different type of products with different layouts we always seem to have this glitch on the SBW CLK line.

The programming works but the data and clock signal integrity suggests its just luck. This can't be expected behavior, any suggestions on what the culprit might be?

Best regards,

Sebastian

  • Anyone from Ti here?

  • I'm no TIer, but...

    I’d expect glitches like this on the data line, as the signal switches direction, so the line is (depending on clock timing) shortly not driven by anyone. The clock, however, is one direction only and shouldn’t have any glitches.

    SBW is very sensitive to signal timing, as there are no control signals for data direction. Line length and capacitance are critical.

  • Yes, its the clock signal that worries me the most. As I said it works right now in the lab pretty much 100% but oscilloscopes suggests that there is an issue.


    With changing conditions, tolerances, mass production it can actually be a huge issue for us, trying to be proactive here.


    When searching the forums here I have not seen this brought up which makes me think this is an issue on our end, but what boggles my mind is that I see this on different setups, different boards etc etc.