This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

The MSP430 output frequency error

Other Parts Discussed in Thread: MSP430G2553, MSP430G2231

The output of MSP430G2231 38KHZ 10% duty cycle, Error in there?

#include <msp430g2553.h>
void main(void){
WDTCTL = WDT_MDLY_32;
IE1 |= WDTIE;
P1DIR |= BIT6;
P1SEL |= BIT6;
TA0CCR0 = 1000;
TA0CCR1 = 100;
TA0CCTL1 = OUTMOD_7;
TA0CTL = TASSEL_1 + MC_1;
_BIS_SR(LPM3_bits + GIE);
}
#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer(void)
{;
}

  • Your question says MSP430G2231. Your code says MSP430G2553. You did not say what chip you were actually using. This is one "Error" or two "Errors".

    Your question says 38KHz. Are you expecting to see 38KHz? Or, did you observe 38KHz?

    Your code is taking ACLK and divide it by 1001. If that produces 38kHz, then ACLK must be slightly over 38MHz, and that is very unlikely.

  • Tell me how I can make the output of 38KHZ 10% duty cycle
  • ACLK is probable to slow to be divided into 38kHz. Try divide SMCLK instead. E.g., for 1MHz, divide it by 26.
  • Well, with 26 ticks per cycle (0..25, so CCR0=25), it would be difficult to get 10% duty cycle, only 7.7 or 11.5% are possible.
    It would be easiest if SMCLK would be 3.8MHz. Then set CCR0=99 and CCR1 can be set to the DC in % (1=1% etc.).
    This is, however, simple math.
  • void main(void)
    {
      WDTCTL = WDTPW + WDTHOLD;
      DCOCTL = CALDCO_1MHZ;
      BCSCTL1 = CALBC1_1MHZ;
      P1SEL = BIT6;
      P1DIR = BIT6;
      P1REN = (P1OUT = (P1IN & ~BIT6));
      P2SEL = 0;
      P2REN = (P2OUT = P2IN & ~BIT2);
      TACCR0 = 26-1;
      TACCR1 = 3;
      TACCTL1 = OUTMOD_7;
      TACTL = TASSEL_2 | MC_1;
      __bis_SR_register(CPUOFF | OSCOFF);
      __no_operation();
       
       for(;;)
      {
        _BIS_SR(LPM3_bits + GIE);
        _NOP();
      }
    }

    11% duty cycle,The high power 15MA, how can I reduce the power consumption, or a 0.1% duty cycle

  • If the device is in LPM3, then the CPU is stopped. The clock system doesn't draw that much, nor do the other internal peripherals, if active at all (let alone the timer). So something else is drawing the current. Maybe your PWM output sources some circuitry that feasts on the PWM signal. If so, use serires resistors to limit the current or something else.
    For 0.1% DC, teh tiemr clock frequency mus tbe 1000 times higher than the desired PWM frequency. For your wanted 38kHz PWM frequency, this would mean 38MHz timer clock, which is outside the specs of the MSP, except for those rare MSPs with TimerD module. However, I don't have any personal experience with TimerD and its high-resolution/high-speed functionality.

**Attention** This is a public forum