This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SPI bit clock not matching datasheet formula MSP430f47187

Hello everyone,

I'm writing a program that does SPI transfers to SRAM using DMA.  I'm a bit puzzled about the behavior I'm seeing.  I set up my processor to run at 16.77216MHz and wanted the SPI clock to run at half that speed (ideally 16MHz as well, but baby steps, as I'm still trying to get 8MHz working properly...)

Here's my clock initialization function:

void clock_init()
{
	// FLL/Clk Setup
	// Gives us ~16MHz MCLK: 32768 Hz * 4 * (127+1) = 16.777216 MHz
	// Gives us ~8MHz MCLK: 32768 Hz * 4 * (63+1) 	= 8.388608 MHz
	SCFI0 = FN_4 | FLLD1 | FLLD_4;
	FLL_CTL0 = DCOPLUS | XCAP0PF;
	FLL_CTL1 &= ~SELS;
	//SCFQCTL = 63; // Value for 8 MHz
	SCFQCTL = 127;  // Value for 16 MHz
}

and this is the SPI initialization section:

    UCA1CTL1 |= UCSWRST;
    UCA1CTL0 |= UCSYNC + UCMST + UCMSB + UCMODE_0 + UCCKPH;
    UCA1CTL0 &= ~UCCKPL;
    UCA1CTL1 |= UCSSEL_2;//+UCSWRST;

    UCA1BR0 |= 0x02;		//SMCLK/2
    UCA1BR1 |= 0x00;
    UCA1CTL1 &= ~UCSWRST;

According to the user guide I'm using (SLAU056l), on page 597 there's is the formula for the SPI clock speed (f_BitClock):

f_BitClock = f_BRCLK/UCBRx

I'm understanding that f_BRCLK is SMCLK which, in my case is identical to MCLK (please correct me if I'm wrong).  This is set to ~16MHz.

UCBRx is (UCA1BR0 + (UCA1BR1 * 256)), which in my case is just 2.  So I'm expecting to see 16MHz/2, or 8MHz for f_BitClock.  However, when I scope out the SPI clock line I'm seeing a frequency of 4.924MHz.  Okaaaay, this is puzzling, but when I switch the processor to 8MHz by changing SCFQCTL to 63, the SPI clock speed makes sense and running at 4MHz.

Why is this not working at 16MHz?

Thanks.

  • Hello G89,

    Your SPI initialization looks correct, one suggestion I would make is to change the operator in lines 7-8 from a bitwise OR to an equal (from "|=" to "="). This is simply logistical and most likely not resulting in the problem you're seeing, but you typically want to assign UCBRx to a specific value in which case the basic assignment is more appropriate. There's also no need to set both FLLD_4 and FLLD1 inside of the SCFI0 register since they both represent the same value (0x80).

    I always like to make sure that my clocks are operating at the expected frequency, if you have pin 1.4 available can you please output SMCLK onto it? Best make sure that ACLK is steady as well, which can be output on pin 1.5. All you need to implement are these two lines:

    P1DIR = BIT4 + BIT5; // P1.4 & P1.5 to output direction
    P1SEL = BIT4 + BIT5; // P1.4 & P1.5 to output SMCLK & ACLK

    Let's ensure that SMCLK & ACLK are as expected before moving on. Out of curiosity is there any specific reason for the SCFQCTL values chosen? It seems that you could make the values 60 and 121 for frequencies closer to 8 and 16 MHz, respectively.

    Regards,
    Ryan

**Attention** This is a public forum