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Advanced SPI Setup For MSP430F5171

Anil Ozyalcin
Intellectual 280 points
Other Parts Discussed in Thread: MSP430F5171

Hello everyone,

I am using an MSP430F5171, and I have UCB0 configured as SPI Master running at 4 Mhz talking to an IMU.

I originally had UCA0 configured as UART talking to a wireless module, but I determined UART was not fast enough for my application so I decided to move on to SPI. The catch is, I need the MSP430 to be an SPI slave. For whatever reason, the wireless module I am interfacing with insists on being the SPI master, so my MSP430 has to be the SPI slave in this application.

So here is my question, is it possible to have UCA0 be configured as SPI slave while having UCB0 configured as SPI Master? The reason I ask is that the slave enable line of UCA0 (UCA0STE) is the same physical pin as the SPI Clock of UCB0 (UCB0CLK) as shown below (P1.3). Can SPI slave be operated at 4 Mhz by the external master? My MSP430F5171 is running at 25 Mhz.

Thanks!

-Anil

  • 0
    Guru 33653 points

    Anil Ozyalcin said:

    I originally had UCA0 configured as UART talking to a wireless module, but I determined UART was not fast enough for my application

    MSP430F5xx Uart, or other side? MSP430F5xx Uart can go (with 24 MHz XT2) over 4 Mbps.

    http://forum.43oh.com/topic/3413-msp430-uart-benchmark/

  • 0 in reply to zrno soli
    Intellectual 280 points
    The bottleneck is the wireless module, it supports 57600 Baud at max over UART. With SPI, it supports 500 Khz/4 Mhz bus speeds. So I want to leverage those higher speeds by using SPI instead of UART.
  • 0
    Intellectual 280 points
    Does anyone have insight on this? I did some more research, and I am thinking about configuring UCA0 as 3-pin SPI Slave, so that it doesn't need the UCA0STE pin. P1.3, which can be mapped to either UCA0STE or UCB0CLK, would be (hopefully) automatically routed to UCB0CLK (datasheet says USCI automatically takes care of it :S ), since UCB0 is a 4-pin SPI master, and needs UCB0CLK.

    From what I understand, 3-pin and 4-pin SPI is identical, aside from the lack of Slave enable/Chip Select in 3-pin mode. I was thinking by going this route, I can use any other GPIO to take care of the incoming Slave enable line for UCA0. Can anyone guide me here? Am I interpreting the datasheet correctly?

    Thanks!
  • 0 in reply to Anil Ozyalcin
    Guru 227245 points
    You are right, 4-pin SPI (actually 4+n pin where n is 1 if slave and the number of slaves when master) is the same as 3-pin but with an additional output driver control line that can be tied to the chip select signal for instant reaction.

    The STE pin is only needed when 1) the MSP is slave and there are other slaves or 2) the MSP is master and there are multiple masters on the bus.
    It simply deactivates the output drivers so the USCI can be instantly silenced if a different slave is selected or a different master wants to take over. if you are the only master or the only salve, you don't need STE.
    In any case, (re)acting or providing a chip select signal by manual I/O operation is mandatory.
    E.g. if you are slave and the chip select goes high, you can reset the USCI and end/abort and high-level protocol.

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