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Clock output after PUC of MSP430F4x

Genius 5960 points
Other Parts Discussed in Thread: MSP430F435

Hi,

I am using the MSP430F435.

I have examined the initial state of MCLK after PUC.

User Guide (SLAU056L) 5.2 FLL + Clock Module Operation (294 pages) is
There are the following description.

=======
After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the
ACLK frequency. When a 32768-Hz crystal is used for ACLK, MCLK and
SMCLK stabilize to 1.048576 MHz.
=======

I am using a crystal of 8MHz to XT1.

Even when using the high-frequency oscillator to XT1,
Do will perform the behavior described in the user guide?

Best Regards,

hamada

  • After a PUC, LFXT1 starts up in low-frequency mode.

    Section 5.2.11 (FLL+ Fail-Safe Operation) says:

    During a LFXT1crystal failure, no ACLK signal is generated and the FLL+ continues to count down to zero in an attempt to lock ACLK and MCLK/(D×[N+1]). The DCO tap moves to the lowest position (SCFI1.7 to SCFI1.3 are cleared) and the DCOF is set.

  • In other words: attaching an HF crystal to XT1 without any other code is like attaching no crystal at all to XT1. The DCO will be adjusted to the lowest possible frequency it can do with the default RSEL setting. To use the crystal, you need to disable the FLL, switch XT1 to high speed and then switch MCLK to XT1 once the crystal has settled.
    If you don't disable the FLL, it will try to adjust the DCO to 8MHz*32, finally bumping the DCO to the maximum speed it can do with the default RSEL setting (see datasheet). In any case, to be able to switch MCLK to the crystal, you'll need to set teh DCO to any value but the lowest or highest, so there is no DCO fault. Else you won't be able to clear OFIFG and MCLK will remain in fallback mode.