MSP430F5310 PMM Setting cause erratic operation with no debugger

I have discovered that when i have disabled the PMM, i got normal operation with or without debugger. Also' i could then activate VCore again. I used TI firmware library:
PMM_disableSvsLSvmL(); // Disable Low side part
PMM_disableSvsHSvmH(); // Disable High side part
PMM_disableSvsLReset();
PMM_disableSvmLInterrupt();
PMM_disableSvsHReset();
PMM_disableSvmHInterrupt();
PMM_clearPMMIFGS();
PMM_setVCore(1); // Do not remove!
PMM_setVCore(0); // Preceed this function with PMM_setVCore(1) !

Note the last two lines - It seems that there may be some problem with the firmware library and i had to add "PMM_setVCore(1) before calling "PMM_setVCore(1);

Hi,
Thanks for your reply. I realize that my original post is confusing: The sentence "-When i disable PMM initialization using the firmware library function PMM_setVCore(1)" was a wrong description. I meant that if i comment out "PMM_setVCore(1)" (so that it is not called at all), then the code executed the same with debugger or without debugger.
Later i understood that PMM supervision is enabled by default, and the fact that i do not call "PMM_setVCore(1)" does not mean VCore supervision is disabled. So i have decided to first disable all PMM functionality and re-enable it again by calling PMM_setVCore(0) ( I decided to use level 0 instead of level1 in setVCore).
At this stage execution with/without debugger was OK, but i still got the SVSL flag set on reset. Only after adding "PMM_setVCore(1)" before the "PMM_setVCore(0)", i got clean reset, which means i will be able to detect Watchdog reset by WDTTO flag or any other reset source. So now i got proper functionality, but it is strange why i have to call PMM_setVCore() twice.
Regarding the information you asked. I can not sent schematics but here is some information: I am using a custom board, powered by 3.6Vdc Lithium battery. A 10 Ohm series resistor connected to Positive battery terminal, creating Vbat. An 470nF capacitor is connected on VCORE pin. AVCC1, DVCC1 and DVCC2 are connected to the Vbat with 200nF bypass capacitor. nReset is connected to Vbat through 100K and to Ground with 1nF capacitor.

Regards,
Alon

Hi Alon,

Using Driverlib you should be able to just call PMM_setVcore(x) with whatever level you want without any issue - you shouldn't have to call setVcore(0) first or disable the SVS or anything - it should all be handled for you by the library already. You mentioned that you are seeing the device unexpectedly reset, and you see SVSL (16h) value being what is in SYSRSTIV - is that correct? That is not expected and would make me suspicious of your board, particularly Vcore. Could you please run your same code on a TI target eval board and see that the issue does not occur? Using an F5329 on the MSP-TS430PN80A board (this is similar to F5310) I could not reproduce the issue so I'd like you to try the same thing on a TI eval board for your device (I'm hoping you have one of these from your early development? ) Because the reset is SVSL meaning low side, I'd be worried about if anything could be interfering with the connections to your Vcore pin (maybe bad solder or something touching)?

In addition, do you set PMM_setVcore(1) before increasing the frequency up to 8MHz? I would recommend this simply because 8MHz is right on the edge of what Vcore = 0 can support, so I could also see you getting resets if your clock setting caused the device to run at a bit above 8MHz. Maybe you should post your clock init code with your PMM code as well.

In addition, regarding your comment about SYSRSTIV - did you know that you can continue to read out SYSRSTIV and it will show you any other lower priority reset interrupt events that were pending? So you ought to still be able to see the WDT reset if it had occurred before the SVSL reset by reading SYSRSTIV multiple times (see section 1.3.7 in the user's guide www.ti.com/lit/pdf/slau208). So you can keep reading it until it becomes 0 to see all pending reset interrupt causes.

Regards,
Katie

Hi Katie,

   Thanks a lot for your detailed answers, it is very helpful !   At this moment i had to skip to another project. I will implement your suggestions when i resume with this project. 

My reply bellow each paragraph:

>>Using Driverlib you should be able to just call PMM_setVcore(x) with whatever level you want without any issue - you shouldn't have to call setVcore(0) first or disable >>the SVS or anything - it should all be handled for you by the library already. You mentioned that you are seeing the device unexpectedly reset, and you see SVSL >>(16h) value being what is in SYSRSTIV - is that correct? That is not expected and would make me suspicious of your board, particularly Vcore. Could you please run >>your same code on a TI target eval board and see that the issue does not occur? Using an F5329 on the MSP-TS430PN80A board (this is similar to F5310) I could >>not reproduce the issue so I'd like you to try the same thing on a TI eval board for your device (I'm hoping you have one of these from your early development? ) >>Because the reset is SVSL meaning low side, I'd be worried about if anything could be interfering with the connections to your Vcore pin (maybe bad solder or >>something touching)?

A: I have this board, will try this when i resume working on the project. Actually the problem i had was not Resets during operation. It was that on normal power reset, i got SVSL value in SYSRSTIV.

>>In addition, do you set PMM_setVcore(1) before increasing the frequency up to 8MHz? I would recommend this simply because 8MHz is right on the edge of what >>Vcore = 0 can support, so I could also see you getting resets if your clock setting caused the device to run at a bit above 8MHz. Maybe you should post your clock init >>code with your PMM code as well.

A:  I have set PMM_setVcore(1 and 0) after setting 8MHz clock. I will try to set it before setting the clock.  See my Init code bellow:

void init_msp(void)
{
  //#######################################  
  //#define INIT_MEMORY_ADDR 0x0900         //errata in revision C !!!!!!!!!!!!!!!
  //  unsigned int *Address = ((unsigned int*)INIT_MEMORY_ADDR);
  //  *Address = 0x9628;
  //  *(Address+4) = 0x0800;
  //  __disable_interrupt();
  //  *Address = 0x9600;
  //###################################
  ID_F = (char*) FSEG_C;
  __disable_interrupt();
  WDTCTL = WDTPW + WDTHOLD;                 // stop wadchdog until stabilization
  P5SEL |= BIT4+BIT5;                       // Port select XT1
  UCSCTL5 |= DIVA_1;                        // ACLK = XT1/2
  UCSCTL6 &= ~(XT1OFF);                     // XT1 On
  UCSCTL6 &= ~XCAP_3;                        //Clear default internal load cap
  UCSCTL6 |= XCAP_3;                        // Set internal load cap
  UCSCTL3 = 0;                              // FLL Reference Clock = XT1
  // DCOCLKDIV source for MCLK,SMCLK
  // Loop until XT1 fault flag is cleared
  do
  {
    UCSCTL7 &= ~XT1LFOFFG;                  // Clear XT1 fault flags
  }while (UCSCTL7&XT1LFOFFG);               // Test XT1 fault flag
 
  //  UCSCTL6 &= ~(XT1DRIVE_3);              // Xtal is now stable, reduce drive strength
  //  UCSCTL6 |= XT1DRIVE_3;                 // SET Xtal to desired drive strength
 
 
  // Initialize DCO to 8 MHz
  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
  UCSCTL1 = DCORSEL_6;                      // Set DCOR for DCO = 8 MHz range
  UCSCTL2 = FLLD_1 + 243;                   // Set DCO Multiplier for 8 MHz
  // (N + 1) * FLLRef = Fdco
  // (243 + 1) * 32768 = 8 MHz
  // Set FLL Div = fDCOCLK/2
 
  __bic_SR_register(SCG0);                  // re-enable the FLL control loop  
 
  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
  __delay_cycles(250000);            // 31 msec
 
  // Loop until XT1 & DCO fault flag is cleared
  do
  {
    UCSCTL7 &= ~(XT1LFOFFG + XT2OFFG + DCOFFG);
    // Clear XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;            // Clear fault flags
  }while (SFRIFG1&OFIFG);         // Test oscillator fault flag
  // timer definitions
  TBCTL = TBSSEL_1+TBCLR;           // ACLK
  TBCCR0 = tictime;              // 1 sec
  TBCCR2 = 0xffff;               // for security
  TBCCTL0 = CCIE;                // enable timer B interrupt
  TBCTL |= MC_2;                // start timer B, continuos mode

  //port definitions
  P1OUT  = BIT5;
  P1DIR |= BIT2+BIT3+BIT4+BIT5+BIT7;    // DIR=1 ==> Output.
  P2OUT =  BIT2+BIT3;  
 
  /* Add_On_GPIO1 (P2.3) if toggled by main board will reset the 3G board */
  P2DIR |= BIT0+BIT1+BIT4+BIT6+BIT7;    // P2.2+P2.3+P2.5 Add_On GPIO's are inputs
  while ( (P2IN&BIT3)==0 );             // Wait till Add_On_GPIO1 goes high
  // Enable P2.3 interrupt Rising Edge interrupt.
  P2IES |= BIT3;                            // Enable Add_On_GPIO1 Falling Edge interrupt
  P2IFG &= ~BIT3;                           // Clear P2.3 IFG interrupt flag
  P2IE |= BIT3;                             // Enable P2.3 interrupt
 
  P3OUT =  0;      
  P3DIR |= BIT3+BIT4;            // UART
  P4OUT = 0;
  P4DIR |= BIT6;
  P5OUT =  0;      
  P5DIR |= BIT0+BIT1+BIT2+BIT3;            //  
  P6OUT  =  BIT7;      
  P6DIR |= BIT4+BIT5+BIT6+BIT7;   
  PJOUT = 0;
  PJDIR = 0xFF;
 
  P4SEL |= BIT0+BIT4+BIT5;                   // SPI
  UCA1CTL1 |= UCSWRST;                      // **Put state machine in reset**
  UCA1CTL0 = UCSYNC|UCCKPL|UCMSB;          // 3-pin, 8-bit SPI slave,
  // Clock polarity high, MSB
  UCA1CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine*
 
//  SetVCoreUp(0);          // Avoid this setting. It generates false SYSRSTIV_SVSL event on reset!
 
#warning Changing section bellow may cause unpredictable operation when executing with out a debugger!
/****************** DO NOT CHANGE PMM SECTION BELLOW !!! **************************/
/*  Setting PMM in a diferent way may cause one of two problems:                  */
/*    1. It may not be able to detect Reset event (Watchdog/Wronf Password/... ). */
/*    2. Firmware may not function properly in stand alone mode with no debugger. */
/*  If PMM is not required at all, remove the two last lines in section bellow:   */
/*   PMM_setVCore(1) and PMM_setVCore(0)                                          */

  PMM_disableSvsLSvmL();        // Disable Low side part
  PMM_disableSvsHSvmH();        // Disable High side part
  PMM_disableSvsLReset();
  PMM_disableSvmLInterrupt();
  PMM_disableSvsHReset();
  PMM_disableSvmHInterrupt();
  PMM_clearPMMIFGS();
  PMM_setVCore(1);              // Do not remove!
  PMM_setVCore(0);              // Preceed this function with PMM_setVCore(1) !
/**********************************************************************************/
 
  __enable_interrupt();                      // Enable interrupts
}                               // end init processor

>>In addition, regarding your comment about SYSRSTIV - did you know that you can continue to read out SYSRSTIV and it will show you any other lower priority reset >>interrupt events that were pending? So you ought to still be able to see the WDT reset if it had occurred before the SVSL reset by reading SYSRSTIV multiple times >>(see section 1.3.7 in the user's guide www.ti.com/lit/pdf/slau208). So you can keep reading it until it becomes 0 to see all pending reset interrupt causes.

A:  I was not aware, I will update my code accordingly.

 

Regards,

Alon

 

 

Hi Alon,

Any update here that you can share? Were you able to figure out your issue?
-Katie

Hi Katie,
I have relocated the initialization of PMM to location before setting the system clocks. It made some improvement - now i did not have to call PMM_setVCore(1) before calling PMM_setVCore(0). So now it looks like:

PMM_disableSvsLSvmL();
PMM_disableSvsHSvmH();
PMM_disableSvsLReset();
PMM_disableSvmLInterrupt();
PMM_disableSvsHReset();
PMM_disableSvmHInterrupt();
PMM_clearPMMIFGS();
////PMM_setVCore(1); // Not necessary any more
PMM_setVCore(0);

I tried removing some of the disable functions and got this combination that still works well in my board:
PMM_disableSvsLSvmL();
PMM_disableSvsLReset();
PMM_disableSvsHReset();
PMM_setVCore(0);

So i still need to call the 3 disable functions preceding PMM_setVCore(0). But i can live with this (no code size problems). I don't have time now to test on the EV board so i will stay with this configuration.
Thank you very much for your great support!


Regards,
Alon