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FMEA of MSP430F6433

Hidetaka
Expert 1080 points
Other Parts Discussed in Thread: MSP430F6433

Hello,

My customer is developing health care products using MSP430F6433. 

They are creating FMEA of MSP430F6433. 

In the process, I have received the inquiry what happens to a damage and functionality when the pin of a table is open. 

Pin Open the Pin
No. Name Damage Functionality Pin Description Comments
23 P2.6/P2MAP6/R03 　 　 General-purpose digital I/O with port interrupt and mappable secondary function, Default mapping: no secondary function, Input/output port of lowest analog LCD voltage (V5) 　
24 P2.7/P2MAP7/
LCDREF/R13		 　 　 General-purpose digital I/O with port interrupt and mappable secondary function,Default mapping: no secondary function, External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)		 　
27 VCORE 　 　 Regulated core power supply (internal use only, no external current loading) 　
28 P5.2/R23 　 　 General-purpose digital I/O
Input/output port of second most positive analog LCD voltage (V2)		 　
76 VSSU 　 　 PU ground supply ( PU.0 and PU.1 are not used. ) 　
80 LDOI 　 　 LDO input ( LDO is not used. ) 　
81 LDOO 　 　 LDO output ( LDO is not used. ) 　
86 VBAK 　 　 Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Recommended Operating Conditions.
(Backup voltage is not supplied.)		 　
87 VBAT 　 　 Backup or secondary supply voltage. If backup voltage is not supplied, connect to DVCC externally.
(Backup voltage is not supplied.)		 　

Moreover, when between the pins of the next table short-circuits, I have received the inquiry what happens to a damage and functionality similarly.

Pin to Pin Short 　 　 　
No. Name Pin Description No. Name Pin Description Damage Functionality Comments
26 DVSS1 Digital ground supply 27 VCORE Regulated core power supply (internal use only, no external current loading) 　 　 　
81 LDOO LDO output 82 NC No connect.(high) 　 　 　
85 P7.3/XT2OUT General-purpose digital I/O
Output terminal of crystal oscillator XT2
(No connect.(high))		 86 VBAK Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Recommended Operating Conditions. 　 　 　
86 VBAK Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Recommended Operating Conditions. 87 VBAT Backup or secondary supply voltage. If backup voltage is not supplied, connect to DVCC externally. 　 　 　

Please let me know in the range to understand. 

Regards, Hidetaka.

  • 0
    TI__Expert 3375 points

    Hello Hidetaka-san,

    It seems that your customer has not experienced a failure, but they are attempting to devise a plan based on feedback from TI to facilitate failure analysis, if and when such a process is needed for their product.  Is that correct?

    For the open pin (Table 1) inquiry, please clarify the following:

    • Are these pins in operation and then opened, or are these pins not connected at any point during operation?
    • For P2.6, P2.7 and P5.2, what is the pin multiplex configuration?
    • If these pins are connected and then opened can you share detail about the expected state of the pin and circuit connected to it before becoming open?

     

    For the shorted pins (Table 2) inquiry, please clarify the following:

    • What is the pin multiplex configuration for P7.3?
    • What capacitance is connected to Vcore?
    • What is the PMMVCORE setting?
    • For these pins can you share detail about the expected state of them (before shorting them), and the circuits connected to them?

     

    What voltage rails are supplied to the MSPF6433?  It would be useful to see your customer's schematics, and we can contact you offline for them since your customer may not be comfortable with posting them to the E2E forum.

     

    Please keep in mind that we may be able to provide some guidance based on experience, but we may not have data matching the exact conditions that your customer might encounter, since this would have dependency on their hardware and system design.

    Best regards,

    AlanL

  • 0 in reply to AlanL
    Expert 1080 points
    Hello, AlanL-san.

    >> It seems that your customer has not experienced a failure, but they are attempting to devise a plan based on feedback from TI to facilitate failure analysis, if and when such a process is needed for their product. Is that correct?

    Yes, It is because it is the rule which creates "Failure Mode and Effect Analysis" in producing commercially.

    >>For the open pin (Table 1) inquiry, please clarify the following:
    >>Are these pins in operation and then opened, or are these pins not connected at any point during operation?

    The Open pin is OPEN in the board. When it is used with OPEN, it is examination of whether a problem occurs.

    >>For P2.6, P2.7 and P5.2, what is the pin multiplex configuration?

    Pin_23 = R03, Pin_24 = R13, Pin_28 = R23.

    >>What is the pin multiplex configuration for P7.3?
    >>What capacitance is connected to Vcore?
    >>What is the PMMVCORE setting?
    >>For these pins can you share detail about the expected state of them (before shorting them), and the circuits connected to them?

    I hear from a customer and answer.

    Regards, Hidetaka.
  • 0 in reply to Hidetaka
    Expert 1080 points
    Hello, AlanL-san.

    I acquired additional information from the customer.

    >>What is the pin multiplex configuration for P7.3?
    P7.3(GPIO:output(high))
    >>What capacitance is connected to Vcore?
    0.47uF
    >>What is the PMMVCORE setting?
    PMMVCORE = 0
    >>For these pins can you share detail about the expected state of them (before shorting them), and the circuits connected to them?
    Their question wants to know the injury in which a device is influenced, when these pins short-circuit.

    >>What voltage rails are supplied to the MSPF6433?
    3.3V

    Please inform me, if there is something required in addition to these pieces of information.

    Regards, Hidetaka.
  • 0 in reply to Hidetaka
    TI__Guru 56685 points

    Hello Hidetaka-san,

    I have some additional comments for you. Please keep in mind these are not directly tested and are our best guesses of what would happen based on the design around the pins and their functions.

    In regards to Table 1:

    P2.6/P2MAP6/R03
    1. If used as port pin an open will lead to the situation that output signals were not seen by circuits connected to this devices or if used as input the device will not react on signals from outside
            2. If used as R03 (LCD pin) the contrast of the display is influenced because the voltage divider will not work anymore.
    P2.7/P2MAP7/
    LCDREF/R13
    1. If used as port pin an open will lead to the situation that output signals were not seen by circuits connected to this devices or if used as input the device will not react on signals from outside
             2. If used as LCDREF/R13 (LCD pin) the contrast of the display is influenced because the voltage divider will not work anymore or the external applied reference voltage is not seen by the LCD controller.
    VCORE
    1. If this pin is open the core LDO will not see the required 470 nF in such case the system might fail operation because in high current situation e.g. during LPM wake up the buffer cap is missing required by the regulate to survive this kind of peak scenarios.
    2. It also has an influence to overshoots on the Vcore pin because the buffer cap will be charged during start-up!
           3. This is a very critical pin an open can lead to complete fail of the whole device.
    P5.2/R23
    1. If used as port pin an open will lead to the situation that output signals were not seen by circuits connected to this devices or if used as input the device will not react on signals from outside
             2. If used as R23 (LCD pin) the contrast of the display is influenced because the voltage divider will not work anymore
    VSSU If open the GND for the LDO is not connected properly which might lead to dysfunction of the LDO
    LDOI
    1. Depends how the device is powered
      1. if powered via LDO the device will not start
    if powered external the LDO output will fail
    LDOO
    1. Depends how the device is powered
      1. if powered via LDO the device will not start because it sees not power
                        b.  if powered external the LDO output will fail and the circuit connected to LDO output will not see a voltage.
    VBAK           1. if open the switchover events between Vbat and DVCC might not work reliable
    VBAT
    1.  the backup system will not be supplied during DVCC fail which will lead to issues of the back-up system
             2. The fail mode also depends how the back-up system is configured.

    Regarding the 2nd table “Moreover, when between the pins of the next table short-circuits, I have received the inquiry what happens to a damage and functionality similarly”

    If DVSS, LDOO, P7.3/XT2OUT or VBAK is really shorted that you will see high amount of current violating the current specification.

    Normally when a short appears the device will stop operation but this is not a must! Here it strongly depends where the damage appears and how heavy it is!
    Also it depends on the power supply if it can drive the current in short circuit scenario!

    I hope this helps!


    Regards,

    JH

  • 0 in reply to Jace H
    Expert 1080 points
    Thanks, Jace-san.

    The customer once entered into investigation with your help.

    Regards, Hidetaka.

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