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Generate a Clock with Msp430f5259 on Pin1.4

Other Parts Discussed in Thread: MSP430F5259

Hello all,

Could I adapt the following code example to have a MClk as output on Pin1.4? Which modification should I do?

Thank's in advance

ip

//******************************************************************************
//   MSP430F525x Demo - Software Toggle P1.1 at Default DCO
//
//   Description: Toggle P1.0 by xor'ing P1.1 inside of a software loop.
//   ACLK is brought out on pin P1.0, SMCLK is brought out on P6.0, and MCLK
//   is brought out on pin P4.7.
//   ACLK = REFO = 32.768kHz, MCLK = SMCLK = Default 1MHz
//
//                 MSP430F525x
//             -----------------
//         /|\|                 |
//          | |             P1.0|-->ACLK
//          --|RST          P4.7|-->MCLK
//            |             P6.0|-->SMCLK
//            |                 |
//            |             P1.1|-->Port Pin
//
//   E. Chen
//   Texas Instruments Inc.
//   August 2013
//   Built with IAR Embedded Workbench v5.52 & Code Composer Studio v5.5
//******************************************************************************
#include <msp430.h>

void main(void)
{
  volatile unsigned int i;

  WDTCTL = WDTPW+WDTHOLD;                   // Stop WDT
  
  PMAPPWD = 0x02D52;                        // Enable Write-access to modify port mapping registers
  P4MAP7 = PM_MCLK;///P4MAP7 = PM_MCLK;
  PMAPPWD = 0;                              // Disable Write-Access to modify port mapping registers
  
  P1DIR |= BIT1;                            // P1.1 output

  P1DIR |= BIT4;                            // ACLK set out to pins
  P1SEL |= BIT4;
  P6DIR |= BIT0;                            // SMCLK set out to pins
  P6SEL |= BIT0;
  P4DIR |= BIT7;                            // MCLK set out to pins
  P4SEL |= BIT7;                              

  while(1)
  {
    P1OUT ^= BIT1;
    __delay_cycles(60000);                  // Delay
  }
}

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