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broblem: MSP430 instruction takes 4000 CPU cycles

Other Parts Discussed in Thread: MSP430F1222


I have a project using MSP430F1222.

CPU oscillator is 6.4MHz. this is the frequency of timer A tick too.

In the ISR of timer A CC0 I measure how many ticks it takes to execute the following code:

CAPTURE_REGISTER += getMaxTime(MIN_CLOCK_HIGH, MIN_DATA_OUT_HOLD_TIME); // set next compare value


static inline void setSCL(void){



static inline u_int_16 getMaxTime(TIMING_PARAMETERS Time1, TIMING_PARAMETERS Time2)


if (TimingParameterInTicks[Time1] > TimingParameterInTicks[Time2]){

return TimingParameterInTicks[Time1];


return TimingParameterInTicks[Time2];



It takes 4300 timer A ticks and I see this period using logic analyzer also.

Too many ticks.

timer A is fed from SMCLK.

what may be the reason?

  • Have you take a look at the assembly code during debug?

  • Thanks for your answer.

    No, I haven't.

    Now, when I look at the disassembly code I see that the number of assembly instructions for the code segment that I measure its execution time is pretty normal.

    About 15 assembly instructions.

    I see that there are 2 CALL instructions.

    I canceled these two functions by replacing their calls with its contents.

    This is the new code segment which I measure its execution time:

    CAPTURE_REGISTER += TimingParameterInTicks[MIN_CLOCK_HIGH]; // set next compare value

    and the disassembly of it is:

    bis.b #0x8, &P1OUT

    add.w &0x22C, &TACCR0

    Now, the above code is measured to have ~3900 timer A ticks.

    I still have the same problem. What  is wrong?

  • I believe the above two assembly code lines should take at most 20 CPU cycles.
    You can confirm this by modifying your code like this:
    1. Set some GPIO (test pin) output to high.
    2. Your code to be tested (SCL_PORT_OUT |= ... and CAPTURE_REGISTER)
    3. Set the test pint to low.
    4. Use oscilloscope to measurement the time test pin is high.
  • Now, I measure the time period of the execution using GPIO pin taht I set before the code and reset after.

    according to the datasheet of the MCU:

    bis.b #0x8, &P1OUT                         - should takes 5 CPU cycles

    add.w &0x22C, &TACCR0              - should takes 6 CPU cycles

    when I measure the time using logic analyzer I get 133 usec for both instructions.

    CPU frequency is 6.4 MHz, so the number of CPU cycles in this period is 133us / (1 / 6.4M) = 851 cycles.

    I still have the problem: 851 >> 11

  • There seems some possibilities:
    1. CPU freq is not 6.4M. You may need to confirm your system clock by checking the register.
    2. Is your VCC sufficient?
  • Measured VCC is 3.32 v.

    My clock registers configuration is:

    BCSCTL2 = (3<<6) | SELS; // LFXT1CLK

    I am using two 20pF capacitors in parallel to the oscillator.

  • 1. Have you checked OFIFG in IFG1. It should be 0. Have you initialized the clock correctly at startup?

    2. You should be able to measure the frequency of SMCLK on "P1.4/SMCLK/TCK", and your SMCLK and MCLK should both be sourced from your external crystal.

    3. Try using DCO as MCLK, and see what happenes.

    Suppose LFXT1CLK doesn't work, MCLK will switch to DCO. Accoding to your setting (DCOx=3, MODx=0, Rsel = 0), and table DCO (Page 23 of SLAS361D), the DCO frequency is about 0.8 - 0.16 M, quite close to your result.

    Good luck.

  • OK. Now , I initiated the crystal oscillator and the execution of the the two assembly instructions decreased significantly from 133 us to 2.2us.

    It seems that the oscillator works now.

    By the way, my project is written in C++.

    this is the code that initiates the oscillator:

    // config clock module
    // ===================

    // initialize crystal oscillator LFXT1CLK
    // ======================================
            "BIC #020h, SR; turn on oscillator"


           u_int_16 i;

                  IFG1 &= ~OFIFG; // clear OFIFG bit
                  for (i=0; i < 255; i++); // delay
            } while (IFG1 & OFIFG);


    BCSCTL2 |= 3<<6; // select LFXT1CLK

    I still have two broblems: 

    2) my osillator is 6.4 MHz. I look at the ACLK signal on pin P2.0/ACLK using the logic analyzer and there the frequency of ACLK if exactly 6MHz 50% duty cycle. Shouldn't it be 6.4 MHz? Why is this difference?

    1) I see that the 2.2us period on the the logic analyzer takes 14 ACLK cycles. MCLK freqency = 1 / (2.2us/14) = 6.3636 MHz. this is very close to 6.4 MHz. is this calculation correct?

    Thank so much for your support.

  • 1. ACLK should show exactly the frequency of LFXT1CLK. So does this mean your crystal frequency is 6M? Or try to check if there is any error in the result in the logic analyzer.

    2. The calculation should be correct. You may also measure more instruction cycles to improve the accuracy.

  • I tried several different oscillators with different frequencies.

    The two of KDS manufacturers are faulty. they don't produce the frequency that is wrriten and their duty cycle is not 50% constantly.

    Now I use 6 MHz oscillator and everything works fine including all the calculations.

    Thanks so much for your help.