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MSP430F2232 Leakage Current

Other Parts Discussed in Thread: MSP430F2232

Ref: MSP430F2232 Rev G. Microprocessor

We have come across an issue.

We have a voltage divider consisting of R1 283Kohm (1W 1%) resistor in series with R2 10Kohm (0.125W 0.1%) resistor.

P2.2 connected to R1-R2 junction. Low side of R2 connected to COM - AVss - DVSS Negative Buss.

With a constant DC Voltage 28.44 is applied +R1 & - R2 COM – Avss – DVSS:

@ 26.4ºC the voltage across R2 measured 0.976 Vdc.

Increasing the Temperature to the Processor

@ 41ºC the voltage across R2 measured 1.050 Vdc.

Result è 11.4ua/18.2ºC {0.626ua/ºC}

 When the processor returns to 26.4ºC, and R2 is 0.976 Vdc

The A/D converter is working properly with correctly digitizing the voltage measured. We think that somehow the P2.2 input is back feeding current into R2. 

In the spec sheet on page 12 the PORTS (P1, P2, P3, and P4) leakage current is ± 50nA MAX @ 25ºC.

What is the Temperature coefficient? We’re seeing 0.626ua/ºC. (Roughly 10x times larger than 50na in 1ºC change)

Is there some way that we have setup/configured the P2.2 port to cause this problem? Its dedicated function is to read the voltage of R2.

Thank you in advance,

Lee Gassaway

  • What "spec sheet" do you mean? The MSP430F2232 datasheet specifies on page 30 that the 50 nA leakage current is measured over all temperatures.

    However, it also says that "the leakage current is measured with VSS or VCC applied to the corresponding pin(s)". Check if larger or smaller levels get different leakage currents.

    What reference voltage are you using?

    Why do you think that the ADC is correctly digitizing the voltage? Did you check with another voltmeter?

  • Lee Gassaway said:
    Is there some way that we have setup/configured the P2.2 port to cause this problem? Its dedicated function is to read the voltage of R2.

    Have you set the ADC10AE0.y control signal for P2.2?

    The Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger section of the MSP430F2232 datasheet contains the note:

    (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

  • Hi,
    If you have configured P2.2 as ADC input you have to consider the ADC input specification and sampling time recommendation. A typical issue is, that your sampling time is to short due to your high impedance input. Please note, that you have to charge an internal sampling capacitance to get the right ADC value.

    Please refer to users guide chapter 22.2.5.1 Sample Timing Considerations on page 538.

    Best regards,
    Tobias

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