MSP430F2471: Pad Logic delay

Kaka

Hi Community member,

Please let me confirm the following question.
[Question]
Do you define the the SPI timing characteristics in consideration of Pad logic delay?

If you have any questions. please let me know.
Best regards.
Kaka

over 10 years ago

0 Evan W over 10 years ago

TI__Mastermind 40610 points

Kaka,

Allow me some time to ask our systems team to understand how our SPI is characterized and tested and whether or not they are in consideration of pad logic delay.

0 Kaka over 10 years ago in reply to Evan W

Guru 24520 points

Hi Evan,
Thank you for your kindly cooperation.
I'm waiting for you updates.

Best regards.
Kaka

0 Evan W over 10 years ago in reply to Kaka

TI__Mastermind 40610 points

Kaka,

From systems: The timings are referenced to the pins i.e. all internal delays should be considered.

0 Kaka over 10 years ago in reply to Evan W

Guru 24520 points

Hi Evan,

Thank you for your update.
I will inform your comments to my customer.

Best regards.
Kaka

0 Evan W over 10 years ago in reply to Kaka

TI__Mastermind 40610 points

Kaka,

Due to inactivity, I'm going to be closing this thread. If you have any followup, please post here and it will reopen.

0 Kaka over 10 years ago in reply to Evan W

Guru 24520 points

Hi Evan,
Thank you for your help.
We got the cooperation form the local TI engineer. And we could close this question.

Best regards.
Kaka

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MSP430F2471: Pad Logic delay