DCO Frequency Accuracy

Other Parts Discussed in Thread: MSP430F5359

I am using an MSP430F5359 with a 32khz watch crystal connected to XT1.  I use the following code to initialize the clocking system:

    while(BAKCTL & LOCKBAK)                    // Unlock XT1 pins for operation
        BAKCTL &= ~(LOCKBAK);
    UCSCTL6 |= XCAP_3;
    UCSCTL6 &= ~(XT1OFF);           // XT1 On
    UCSCTL3 = 0;                              // FLL Reference Clock = XT1
    __bis_SR_register(SCG0);          // Disable the FLL control loop
    // Initialize DCO to 20MHz  
    UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_6;               // Select DCO range 40MHz operation
    UCSCTL2 |= FLLD_1 + 609;             // Set DCO Multiplier for 20MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (609 + 1) * 32768 = 19.988MHz
                                            // Set FLL Div = fDCOCLK/2
    __bic_SR_register(SCG0);                  // Enable the FLL control loop
    // Worst-case settling time for the DCO when the DCO range bits have been
    // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
    // UG for optimization.
    // 32 x 32 x CPUFREQ * 1 MHz / 32,768 Hz = MCLK cycles for DCO to settle
    __delay_cycles(32 * 32 * 20000000UL / 32768);
    
    // Loop until XT1,XT2 & DCO fault flag is cleared
    do
    {
        UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                                // Clear XT2,XT1,DCO fault flags
        SFRIFG1 &= ~OFIFG;                      // Clear fault flags
    }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

With all that, and then routing the SMCLK out to a GPIO pin, I observe a clock frequency of 20.98MHz rather than the expected 19.98MHz.  Is the frequency really supposed to be off by that much?  Will the frequency be consistent from MSP to MSP?

Thanks,

Chris