configure DCO manually in the chip MSP430F5*** ( FLL is disabled)

The DCO just starts at RSEL=2, DCO=0, MOD=0, which can be anywhere between 320 kHz and 750 kHz. It then gets adjusted by the FLL until it is at 64 times the REFO frequency.

And there is no real calculation. The FLL just counts how many DCO cycles happen during one REFO cycle. If the number is smaller or larger than 64, DCO/MOD get incremented/decremented.

Hi Ladisch,

Clemens Ladisch said:

The DCO just starts at RSEL=2, DCO=0, MOD=0, which can be anywhere between 320 kHz and 750 kHz. It then gets adjusted by the FLL until it is at 64 times the REFO frequency.

as the spec said 'When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, '  it should between 750kHz and 3.17MHz when  RSEL=2.

 

Clemens Ladisch said:

And there is no real calculation. The FLL just counts how many DCO cycles happen during one REFO cycle. If the number is smaller or larger than 64, DCO/MOD get incremented/decremented.

I don't care about how FLL is working, what I want to know is how to  configure the DCO & MOD manually to get the designed MCLK while FLL is closed, just like 2.097152 MHz.  As you mentioned , it has to wait for many DCO cycles when FLL is enable to generate MCLK, I don't want to wait such a long time that's why disable the FLL. I think there is a way to do it, but I don't know how to calculate to get the DCO & MOD.

 

it should between 750kHz and 3.17MHz when RSEL=2

What I quoted is the possible range for DCO=0. When you set RSEL=2 and DCO=0, one chip might run at 320 kHz, while another might run at 750 kHz.

For RSEL=2, trhe possible range for all DCO values is from 320 kHz to 7.38 MHz. The guaranteed range is from 750 kHz to 3.17 MHz.

When you want to run at a specific frequency, you must use the MAX value of the lowest DCO setting and the MIN value of the highest DCO setting to ensure that  every chip can run at a frequency in this range.

it has to wait for many DCO cycles when FLL is enable to generate MCLK, I don't want to wait such a long

If there were a faster way, the chip would be already doing it.

You could measure your chip once, and store the required RSEL/DCO/MOD values in flash. And then hope that your chip always runs at the same temperature and supply voltage, and that aging doesn't change it too much.
Otherwise, you have no choice but to compare the DCO against a known reference clock.

If you want to set the DCO manually to, for example, 2.097152 MHz; this is how to do it step by step:

(1) Disable FLL.

(2) Select the lowest DCORSELx setting so that the DCO is able to generate the desired frequency. In this, the proper setting is 2.

(3) Set DCO and MOD according to your best guess. For example, the mid-point, 15 and 15 respectively.

(4) Measure the resulting DCO frequency and compare that with your desired frequency, i.e., 2.097152 MHz in this case.

(5a) If the resulting DCO frequency is too low, you increase the current MOD -- in case the current MOD is 31, you change it to 1 and increase the current DCO.

(5b) If the resulting DCO frequency is too high, you decrease the current MOD -- in case the current MOD is 0, you change it to 30 and dencrease the current DCO.

(5c) If the resulting DCO frequency is exactly right (this rarely, if ever, happens in real life), you smile.

(6) After step (5a), (5b) or (5c), go back to step (4).

Note that this is a never ending task but you did your best and the resulting frequency is as close to what you desired as possible.

Note also that FLL is trying to do steps (4) through (6) for you automatically. But you choose to do it yourself.

Clemens Ladisch said:

You could measure your chip once, and store the required RSEL/DCO/MOD values in flash. And then hope that your chip always runs at the same temperature and supply voltage, and that aging doesn't change it too much.

Thank you for your suggestion.

That's what I am doing now, but I want to know if a const could be configured in all chips,as said before,UCSCTL0 = 0x14B8 (DCO=0x14, MOD=0x17 ) for  fDCO = 2.097152 MHz. In this way, what's the tolerance? suppose that the temperature and voltage is not changed.

Still I want to know if DCO & MOD could be calculated. I try to verify it but fail. 

verify process:

1) fDCO = 0.75+20*(3.17-0.75)/32 = 1.5125MHz (DCO=0x14), fDCO+1 = 1.588125MHz

2)  modulator mixing formula:  t = (32 – MOD) × tDCO + MOD × tDCO+1

As above, the final fDCO = ((32-23)*fDCO + 23*fDCO)/32 = 1.566855MHz (MOD =0x17), the result is not expected 2.097152MHz

what's wrong ?

Anyway to calculate to get the DCO & MOD? which will simplify the process.

The calculation is very simple indeed. The result will be +/- 10% accurate. In a lot of applications, that is good enough.
To use FLL is very simple too. The result can be better than +/- 1% accurate. In some applications, that is still not good enough.
Use an external clock signal or a crystal with the desired frequency are feasible too. You can get an accuracy of a few parst per million.
Choose your own poison ;)

old_cow_yellow said:

The calculation is very simple indeed. The result will be +/- 10% accurate.

As mentioned above, I'm trying to calculate but fail. Could you share me the calculation or verify the DCO configuration?

(fDCO = 2.097152 MHz while UCSCTL0 = 0x14B8; UCSCTL1 = DCORSEL_2; )

Perry said:

(fDCO = 2.097152 MHz ...

As I told you, at best, you can get something like fDCO = 2.097152 +/- 10. That is, somewhere between 1.9 MHz and 2.3 MHz.

Perry said:

... while UCSCTL0 = 0x14B8; UCSCTL1 = DCORSEL_2; )

Well, if you use those settings, the fDCO can be calculated (very simply). Here it is:

(1) Your setting is: DCORSEL = 2, DCO = 20 (0x14), MOD = 20 (0xB8>>3).

(2) From the DCO Frequency Section of the Data-Sheet of the chip you use, you can find the values of fDCO(2,31) and SDCO

(3) Thus fDCO(2,21) = fDCO(2,31) / SDCO ** (31-21)

(4) fDCO(2,20) = fDCO(2,21) / SDCO

(5) The resulting fDCO is a mixture of 20 cycles of fDCO(2,21) and 32-20=12 cycles of fDCO(2,20)

As you can see, there are a lot of uncertainties in the values form the Data-Sheet, there is a lot of uncertainties in the result of the calculations as well. I said +/- 10%, it could be much higher. 

I want to know if a const could be configured in all chips […] what's the tolerance?

As shown in the datasheet for, e.g., the constant values RSEL=2/DCO=0/MOD=0, the possible range is 320 kHz to 750 kHz. Relative to the lower limit, this is a tolerance of 134 % over all supply voltages and temperatures.

If we assume the temperature drift and voltage drift values are accurate (which they aren't), then the possible range at 25 °C and 3.0 V is from 320 kHz × (1 + (0.1 %/°C × (25 °C − −40 °C)) × (1 + (1.9 %/V × (3.0 V − 1.8 V)) to 750 kHz × (1 + (0.1 %/°C × (25 °C − 85 °C)) × (1 + 1.9 %/V × (3.0 V − 3.6 V)), i.e., from 410 kHz to 697 kHz. Relative to the lower limit, this is a tolerance of only 70 %.

In other words, forget about using a constant value for different chips.