MSP430FR5859 ResetsWhen MCLK references DCO @ 16MHz

I am trying to run a project from the ti driverlib examples (Code provided below). The code sets the DCOCLK to 16Mhz, then sets the MCLK and SMCLK to reference the DCOCLK. When the MCLK is set to reference the DCOCLK, an interrupt is hit at 0xFFFA (User NMI) and the system runs back to main. This loop continues indefinitely. The code works fine with the DCOCLK is set to 8MHz, and there is also no issue seen when SMCLK is set to 16MHz. Unfortunately, we really need the burst performance of 16MHz, and wouldn't be able to use 8MHz in the final product.

#include "driverlib.h"

uint32_t clockValue;

void main(void)
{
//Stop WDT
WDT_A_hold(WDT_A_BASE);
//Set DCO frequency to 16MHz
CS_setDCOFreq(CS_DCORSEL_1, CS_DCOFSEL_4);

CS_initClockSignal(CS_SMCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);

//Set wait state to 1
FRAMCtl_configureWaitStateControl(FRAMCTL_ACCESS_TIME_CYCLES_1);

//Set P2.0 as Output Low (for setup as ACLK).
/*

* Select Port 2
* Set Pin 0 to output Low.
*/
GPIO_setOutputLowOnPin(
GPIO_PORT_P3,
GPIO_PIN4
);

//Set P2.0 as Ternary Module Function Output.
/*

* Select Port 2
* Set Pin 0 to output Ternary Module Function, (ACLK).
*/
GPIO_setAsPeripheralModuleFunctionOutputPin(
GPIO_PORT_P3,
GPIO_PIN4,
GPIO_TERNARY_MODULE_FUNCTION
);

/*
* Disable the GPIO power-on default high-impedance mode to activate
* previously configured port settings
*/
PMM_unlockLPM5();

while(1)
{
;
}
}

void CS_initClockSignal(uint8_t selectedClockSignal,
uint16_t clockSource,
uint16_t clockSourceDivider)
{
//Verify User has selected a valid Frequency divider
assert(
(CS_CLOCK_DIVIDER_1 == clockSourceDivider) ||
(CS_CLOCK_DIVIDER_2 == clockSourceDivider) ||
(CS_CLOCK_DIVIDER_4 == clockSourceDivider) ||
(CS_CLOCK_DIVIDER_8 == clockSourceDivider) ||
(CS_CLOCK_DIVIDER_16 == clockSourceDivider) ||
(CS_CLOCK_DIVIDER_32 == clockSourceDivider)
);

// Unlock CS control register
HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY;

switch(selectedClockSignal)
{
case CS_ACLK:
assert(
(CS_LFXTCLK_SELECT == clockSource) ||
(CS_VLOCLK_SELECT == clockSource) ||
(CS_LFMODOSC_SELECT == clockSource)
);

clockSourceDivider = clockSourceDivider << 8;
clockSource = clockSource << 8;

HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELA_7);
HWREG16(CS_BASE + OFS_CSCTL2) |= (clockSource);
HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVA0 + DIVA1 + DIVA2);
HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider;
break;
case CS_SMCLK:
assert(
(CS_LFXTCLK_SELECT == clockSource) ||
(CS_VLOCLK_SELECT == clockSource) ||
(CS_DCOCLK_SELECT == clockSource) ||
(CS_HFXTCLK_SELECT == clockSource) ||
(CS_LFMODOSC_SELECT == clockSource)||
(CS_MODOSC_SELECT == clockSource)
);

clockSource = clockSource << 4;
clockSourceDivider = clockSourceDivider << 4;

HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELS_7);
HWREG16(CS_BASE + OFS_CSCTL2) |= clockSource;
HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVS0 + DIVS1 + DIVS2);
HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider;
break;
case CS_MCLK:
assert(
(CS_LFXTCLK_SELECT == clockSource) ||
(CS_VLOCLK_SELECT == clockSource) ||
(CS_DCOCLK_SELECT == clockSource) ||
(CS_HFXTCLK_SELECT == clockSource) ||
(CS_LFMODOSC_SELECT == clockSource)||
(CS_MODOSC_SELECT == clockSource)
);

HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELM_7);
HWREG16(CS_BASE + OFS_CSCTL2) |= clockSource;
HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVM0 + DIVM1 + DIVM2);
HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider;
break;
}

// Lock CS control register
HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00;
}