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MSP430FR6989 interrupt flag clarification

Paul Schoenke
Expert 1375 points
Other Parts Discussed in Thread: MSP430FR6989, MSP430FR6979

Hello TI E2E forum:

I am looking for some documentation / CCS clarification.  I'm trying to initialize an MSP430FR6989 for my design.  The User guide  shows that there are interrupts on all GPIO ports and shows the address for the interrupt flags for each port (e.g. P1IFG), but the Code Composer “Include” file (msp430fr6979.h) does not define P5IFG, nor P6IFG-P10IFG. 

Are they missing from the chip or from the documentation?

I am planning to use the 100-pin version so it should have all the options in this family. 

Any feedback or input on this is welcomed and appreciated!

Thanks again!

Paul

  • 0
    TI__Genius 17175 points

    Paul,

    The nomenclature is as such: P1IFG.0 represents the first pin (pin 0) or the first port (port 1). Looking in this document (http://www.ti.com/lit/ds/symlink/msp430fr6989.pdf) on page 79, the MSP430FR6989 only supports edge-selectable interrupts for all pins of ports P1, P2, P3 and P4. This is why the header is missing P5IFG-P10IFG, this device does not have interrupt capability on the pins of these ports.

  • 0 in reply to Sean Bigley
    Expert 1375 points

    Thanks much!  The document, SLAU367G, seems to say they exist:

  • 0 in reply to Paul Schoenke
    Guru 74080 points

    Hi Paul!

    The document SLAU367 is the User's Guide for all processors of the FR58xx, FR59xx, FR68xx and FR69xx series microcontrollers. It covers all functions that at least one of the processors of this group supports (or might support in the future). But each processor has it's own datasheet (or there is a smaller subgroup that shares one) - this datasheet contains the information for the processor you are using and it overrules the User's Guide. So if the datasheet says that the MSP430FR6989 has interrupt capable pins at port 1, 2, 3 and 4, the additional information given in the User's Guide doesn't count anymore.

    Dennis

  • 0 in reply to Dennis Eichmann
    TI__Genius 17175 points

    MSP team,


    Do any of the processors mentioned in SLAU367 have interrupt capability beyond GPIO ports 1-4? A cursory look leads me to believe there aren't any currently available. Are there plans to release devices in the future that align with the information given in the User's Guide?

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