IAR error when using MSPware for Watchdog

Hi Jim,

I'm assuming you're using the MSP432 here. What version of IAR and MSPWare are you using? If you're using a LaunchPad, is it Rev1.0 or Rev2.0? Could you please post an image of the errors? Which code example are you using?

This should help us narrow down your issue.

Regards,

James
MSP Customer Applications

Hi Jim,

Thanks for providing details about your work space.

Like you pointed out and according to Table 15-1 in the Technical Reference Manual, the proper clock sources are SMCLK, ACLK, VLOCLK, and BCLK. I'm using MSPWare v3_30_00_18, and I don't see "WDT_A_CTL_SSEL_4" as a #define in 'msp432p401r.h' (found at C:\ti\msp\MSPWare_3_30_00_18\driverlib\inc for me).

/******************************************************************************
* WDT_A Bits
******************************************************************************/
/* WDT_A_CTL[IS] Bits */
#define WDT_A_CTL_IS_OFS                         ( 0)                            /**< WDTIS Bit Offset */
#define WDT_A_CTL_IS_MASK                        ((uint16_t)0x0007)              /**< WDTIS Bit Mask */
#define WDT_A_CTL_IS0                            ((uint16_t)0x0001)              /**< IS Bit 0 */
#define WDT_A_CTL_IS1                            ((uint16_t)0x0002)              /**< IS Bit 1 */
#define WDT_A_CTL_IS2                            ((uint16_t)0x0004)              /**< IS Bit 2 */
#define WDT_A_CTL_IS_0                           ((uint16_t)0x0000)              /**< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
#define WDT_A_CTL_IS_1                           ((uint16_t)0x0001)              /**< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
#define WDT_A_CTL_IS_2                           ((uint16_t)0x0002)              /**< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
#define WDT_A_CTL_IS_3                           ((uint16_t)0x0003)              /**< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
#define WDT_A_CTL_IS_4                           ((uint16_t)0x0004)              /**< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
#define WDT_A_CTL_IS_5                           ((uint16_t)0x0005)              /**< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
#define WDT_A_CTL_IS_6                           ((uint16_t)0x0006)              /**< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
#define WDT_A_CTL_IS_7                           ((uint16_t)0x0007)              /**< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
/* WDT_A_CTL[CNTCL] Bits */
#define WDT_A_CTL_CNTCL_OFS                      ( 3)                            /**< WDTCNTCL Bit Offset */
#define WDT_A_CTL_CNTCL                          ((uint16_t)0x0008)              /**< Watchdog timer counter clear */
/* WDT_A_CTL[TMSEL] Bits */
#define WDT_A_CTL_TMSEL_OFS                      ( 4)                            /**< WDTTMSEL Bit Offset */
#define WDT_A_CTL_TMSEL                          ((uint16_t)0x0010)              /**< Watchdog timer mode select */
/* WDT_A_CTL[SSEL] Bits */
#define WDT_A_CTL_SSEL_OFS                       ( 5)                            /**< WDTSSEL Bit Offset */
#define WDT_A_CTL_SSEL_MASK                      ((uint16_t)0x0060)              /**< WDTSSEL Bit Mask */
#define WDT_A_CTL_SSEL0                          ((uint16_t)0x0020)              /**< SSEL Bit 0 */
#define WDT_A_CTL_SSEL1                          ((uint16_t)0x0040)              /**< SSEL Bit 1 */
#define WDT_A_CTL_SSEL_0                         ((uint16_t)0x0000)              /**< SMCLK */
#define WDT_A_CTL_SSEL_1                         ((uint16_t)0x0020)              /**< ACLK */
#define WDT_A_CTL_SSEL_2                         ((uint16_t)0x0040)              /**< VLOCLK */
#define WDT_A_CTL_SSEL_3                         ((uint16_t)0x0060)              /**< BCLK */
#define WDT_A_CTL_SSEL__SMCLK                    ((uint16_t)0x0000)              /**< SMCLK */
#define WDT_A_CTL_SSEL__ACLK                     ((uint16_t)0x0020)              /**< ACLK */
#define WDT_A_CTL_SSEL__VLOCLK                   ((uint16_t)0x0040)              /**< VLOCLK */
#define WDT_A_CTL_SSEL__BCLK                     ((uint16_t)0x0060)              /**< BCLK */
/* WDT_A_CTL[HOLD] Bits */
#define WDT_A_CTL_HOLD_OFS                       ( 7)                            /**< WDTHOLD Bit Offset */
#define WDT_A_CTL_HOLD                           ((uint16_t)0x0080)              /**< Watchdog timer hold */
/* WDT_A_CTL[PW] Bits */
#define WDT_A_CTL_PW_OFS                         ( 8)                            /**< WDTPW Bit Offset */
#define WDT_A_CTL_PW_MASK                        ((uint16_t)0xFF00)              /**< WDTPW Bit Mask */

From your version to my version on MSPWare, this must have been fixed. However, in 'wdt_a.h' (found at C:\ti\msp\MSPWare_3_30_00_18\driverlib\driverlib\MSP432P4xx for me), I do see "XCLK" and "WDT_A_CTL_SSEL_4".

#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__

//*****************************************************************************
//
//! \addtogroup wdt_api
//! @{
//
//*****************************************************************************

//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif

#include <msp.h>
#include <stdint.h>
#include "sysctl.h"

#define WDT_A_HARD_RESET SYSCTL_HARD_RESET
#define WDT_A_SOFT_RESET SYSCTL_SOFT_RESET

//*****************************************************************************
//
// The following are values that can be passed to the clockSelect parameter for
// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
//
//*****************************************************************************
#define WDT_A_CLOCKSOURCE_SMCLK                                     (WDT_A_CTL_SSEL_0)
#define WDT_A_CLOCKSOURCE_ACLK                                      (WDT_A_CTL_SSEL_1)
#define WDT_A_CLOCKSOURCE_VLOCLK                                    (WDT_A_CTL_SSEL_2)
#define WDT_A_CLOCKSOURCE_XCLK                                      (WDT_A_CTL_SSEL_3)
#define WDT_A_CLOCKSOURCE_BCLK                                      (WDT_A_CTL_SSEL_4)

//*****************************************************************************

I'll submit a bug to fix this. Thanks for bringing it to our attention! In the meantime, which file is shown in your screenshot above? It looks like a code example, and I see it's using "WDT_A_CTL_SSEL_4", which we should fix too.

Regards,

James

MSP Customer Applications