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MSP430F5636 Flash Banks

ducky35061
Mastermind 36545 points
Other Parts Discussed in Thread: MSP430F5636

Can you please tell me if their is any blocking behavior during the erase OR write procedure on MSP430F5636 when executing code from the alternate flash bank.

Does CPU activity at any point stall in Bank 0 during either erase OR write on Bank 1 and vice versa. I appreciate that ISR will be compromised while erasing Bank 0 containing the vector table.

  • 0
    TI__Guru 68116 points
    Hi,

    I checked the user's guide www.ti.com/.../slau208. Table 7-1 Supported Simultaneous Code Execution and Flash Operations, and Table 7-4 Flash Access While Flash is Busy both provide good information about this. Basically, you can do a Bank erase of one bank while executing from the other bank (would have to make sure all your code is in the bank not being erased). However, if you do a segment erase, even if it is a segment in the other bank from where you code is executing, it will be blocking (CPU will wait for segment erase to complete - see section 7.3.1.4 Initiating Erase From Flash). Additionally, if you try to do any write to flash it doesn't matter what bank it is in, if you initiate the write from flash it will be blocking and hold the CPU until the write completes - see section 7.3.2.1 Byte or Word Write. There are different conditions if you initiate write or erase from RAM and are executing from RAM but I assumed in all of these that they were initiating from Flash since they were talking about running from the other bank.

    I think the two tables I mentioned at the beginning give the best overall summary.

    Could you maybe elaborate on what they are trying to do? Some sort of field firmware update?

    Regards,
    Katie
  • 0 in reply to Katie Pier
    TI__Mastermind 36545 points

    Katie, thanks for the clarification and the customer is happy with the response so we can close this thread.

    Steve

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