MSP430F5435a - reset cause

Hello Antoine,

On some other devices, a value of 0x1C in the SYSRSTIV register indicates a PLL unlock (PUC) reset. This does not make much sense seeing as how the MSP430F5435a does not have a USB peripheral. Here is a previous thread of a similar issue: e2e.ti.com/.../311940

Are you able to easily reproduce this behavior, and what is done in the device firmware before a reset occurs in these instances? Can you provide a simple code example that demonstrates the problem? Are you using a TI EVM or custom PCB?

Regards,
Ryan

Hello Ryan,

I don't undersand why MSP430F5435a has no FLL ?

In this document "http://processors.wiki.ti.com/index.php/Handling_MSP430_System_Reset_Events"

case SYSRSTIV_FLLUL: break; // SYSRSTIV : FLL unlock)

I can not easily reproduce the issue, that 's why I don't know what sw behavior occurs before the reset.

In any case what could explain this behavior ?

I use a custom PCB.

Regards,

Hi Antoine,

I will have to check with the Design and Technical Documents Teams to confirm the purpose and operation of a 0x1C value inside of SYSRSTIV. However the MSP430F5435a does indeed have a FLL and an unlock condition is most likely causing the reset behavior you've described. Can you share your UCS initialization code? It is important that the clock system be setup with the correct sequence or unpredictable operation could occur. You may also want to compare the output MCLK frequency vs your expected value and check the FLL-related device errata UCS7 & UCS10.

Regards,
Ryan

Hello Ryan, 

did you have time to see with the design team the purpose of a 0x1CV value in SYSRSTIV ?

Thank you for your help

Regards,

As stated above, there is a possibility that your FLL is unlocking and causing the reset behavior described. You need to evaluate your PMM and UCS registers to make sure that the device is operating within specifications.

Regards,
Ryan

Hello Ryan,

As described in erratasheet, UCS7 and USC10 errata do not  cause a reset. I evaluated the PMM and USC register, but I didn't see any isssue.

I have the following code to configure the UCS module (the first called fucntion is "set_clocks_speed")

void set_clocks_speed(void)
{

    halBoardStartXT1();    
    halBoardSetSystemClock();
}



void halBoardStartXT1(void)
{
  // Set up XT1 Pins to analog function, and to lowest drive    
  P7SEL |= 0x03;                            
  UCSCTL6 |= XCAP_3 ;                       // Set internal cap values
 
  while(SFRIFG1 & OFIFG) {                  // Check OFIFG fault flag
    while ( (SFRIFG1 & OFIFG))              // Check OFIFG fault flag
    {    
      // Clear OSC fault flags
      UCSCTL7 &= ~(DCOFFG + XT1LFOFFG + XT1HFOFFG + XT2OFFG);
      SFRIFG1 &= ~OFIFG;                    // Clear OFIFG fault flag
    }
    UCSCTL6 &= ~(XT1DRIVE1_L+XT1DRIVE0);    // Reduce the drive strength
  }
}



/**********************************************************************//**
 * @brief  Set function for MCLK frequency.
 *
 * @param  none
 *
 * @return none
 *************************************************************************/
void halBoardSetSystemClock(void)
{
    unsigned char setDcoRange, setVCore;
    unsigned int  setMultiplier;

    setDcoRange = DCORSEL_16MHZ;    //0x0050
    setVCore = VCORE_16MHZ;                 //0x0001
    setMultiplier = DCO_MULT_16MHZ;   //488
        
  halBoardSetVCore( setVCore );   

  __bis_SR_register(SCG0);                  // Disable the FLL control loop    
  UCSCTL0 = 0x00;                           // Set lowest possible DCOx, MODx
  UCSCTL1 = setDcoRange;                    // Select suitable range
 
  UCSCTL2 = setMultiplier + FLLD_0;         // Set DCO Multiplier   FLLD_0 = 0
  UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV  |  SELM__DCOCLKDIV ;
  UCSCTL8 |= SMCLKREQEN;
  __bic_SR_register(SCG0);                  // Enable the FLL control loop
 
  // Loop until XT1,XT2 & DCO fault flag is cleared
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
 
  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_FLL_reference. See UCS chapter in 5xx UG
  // for optimization.
  // 32 x 32 x / f_FLL_reference (32,768 Hz) = .03125 = t_DCO_settle
  // t_DCO_settle / (1 / 25 MHz) = 781250 = counts_DCO_settle
  __delay_cycles(781250);  
}




/**********************************************************************//**
 * @brief  Increments the VCore setting.
 *
 * @param  level The target VCore setting
 *
 * @return none
 *************************************************************************/
static void halBoardSetVCoreUp (unsigned char level)
{
  // Open PMM module registers for write access
  PMMCTL0_H = 0xA5;                         
 
  // Set SVS/M high side to new level
  SVSMHCTL = (SVSMHCTL & ~(SVSHRVL0*3 + SVSMHRRL0)) | \
             (SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level);
 
  // Set SVM new Level    
  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;       
  // Set SVS/M low side to new level
  SVSMLCTL = (SVSMLCTL & ~(SVSMLRRL_3)) | (SVMLE + SVSMLRRL0 * level);
   
  while ((PMMIFG & SVSMLDLYIFG) == 0);      // Wait till SVM is settled (Delay)
  PMMCTL0_L = PMMCOREV0 * level;            // Set VCore to x
  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);        // Clear already set flags
 
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);     // Wait till level is reached
 
  // Set SVS/M Low side to new level
  SVSMLCTL = (SVSMLCTL & ~(SVSLRVL0*3 + SVSMLRRL_3)) | \
             (SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level);
 
  // Lock PMM module registers from write access
  PMMCTL0_H = 0x00;                         
}

/**********************************************************************//**
 * @brief  Decrements the VCore setting.
 *
 * @param  level The target VCore.  
 *
 * @return none
 *************************************************************************/
static void halBoardSetVCoreDown(unsigned char level)
{
  // Open PMM module registers for write access
  PMMCTL0_H = 0xA5;                         
 
  // Set SVS/M low side to new level
  SVSMLCTL = (SVSMLCTL & ~(SVSLRVL0*3 + SVSMLRRL_3)) | \
             (SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level);
 
  while ((PMMIFG & SVSMLDLYIFG) == 0);      // Wait till SVM is settled (Delay)
  PMMCTL0_L = (level * PMMCOREV0);          // Set VCore to new level
  // Lock PMM module registers for write access
 
  PMMCTL0_H = 0x00;                         
}

/**********************************************************************//**
 * @brief  Set function for the PMM core voltage (PMMCOREV) setting
 *
 * @param  level Target VCore setting
 *
 * @return none
 *************************************************************************/
void halBoardSetVCore(unsigned char level)
{
  unsigned char actLevel;


    do {
      actLevel = PMMCTL0_L & PMMCOREV_3;
      if (actLevel < level)
        halBoardSetVCoreUp(++actLevel);               // Set VCore (step by step)
      if (actLevel > level)
        halBoardSetVCoreDown(--actLevel);             // Set VCore (step by step)
    }while (actLevel != level);  

}

From Figure 5-1 of the Datasheet, a system frequency of 16 MHz requires a PMMCOREVx setting of at least two. Your code appears to only go up one level. Since we suspect FLL failure I also recommend analyzing your LFXT, including reviewing the board design (SLAA322), ensuring the proper load capacitor values are used (external is more reliable than internal), and maintaining a high drive strength.

Regards,
Ryan