Hi,
I took EVB of CC4306147 with code example that operate MCLK in 2.45MHz by external crystal 32.768KHz + FLL
and i have measured the MCLK by oscilloscope and i notice a jitter of 10nS, i have measured the the ACLK and the 32.768KHz is look very good.
Do you see any problem with the code?
Is this jitter is normal?
by the way i would like to work in MCLK of 4.194MHz for UART purpose (less error) , i have changed the code with 2 these lines marked in blue in the code, and i got 4.194MHz with jitter
is it OK ? or i need to change more value in the code
Thanks Hadi
see code below:
#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
P1DIR |= BIT0; // P1.0 output
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP0 = PM_ACLK; // Map ACLK output to P2.0
P2MAP2 = PM_MCLK; // Map MCLK output to P2.2
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT0 + BIT2; // ACLK, MCLK, SMCLK set out to pins
P2SEL |= BIT0 + BIT2; // P2.0,2 for debugging purposes.
// Initialize LFXT1
P5SEL |= 0x03; // Select XT1
UCSCTL6 |= XCAP_3; // Internal load cap
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
}while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag
// Initialize DCO to 2.45MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz
UCSCTL2 = FLLD_1 + 74; // Set DCO Multiplier for 2.45MHz
// UCSCTL2 = FLLD_1 + 127; // Set DCO Multiplier for 4.194MHz
// (N + 1) * FLLRef = Fdco
// (74 + 1) * 32768 = 2.45MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 2.45 MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle
__delay_cycles(76563);
// __delay_cycles(131072);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
while(1)
{
P1OUT ^= BIT0; // Toggle P1.0
__delay_cycles(600000); // Delay
}
}
