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MSP430AFE233: Absolute maximum voltage with PGA gain greater than 1

Part Number: MSP430AFE233

What is the maximum allowable voltage on analogue inputs (measured between pin and VSS) of SD24 inside MSP430AFE2xx, especially when PGA gain is set to values different than default 1?

I've read the datasheet, but I'm still confused about that. Differential full scale input voltage range should be between -Vref/2GAIN and +Vref/2GAIN. For GAIN = 1 we have +/-500mV, and for example for GAIN = 32 we have +/-15mV. I have a signal which sometimes is around 300mV and sometimes around 3mV, so I'd like to implement autoranging, when I measure the signal with GAIN = 32 and detect overflow (SD24_MEM constantly at 0xFFFF) the PGA should change to GAIN = 1, and then if measured voltage is below some value, the PGA should back to GAIN = 32.

The question is: what will happen if I set GAIN = 32 and then apply 300mV voltage on SD_24 input pin? Will it lead only to overflow of SD24_MEM register or physical damage of the input? I assume that until voltage at the pin not exceed Absolute ratings there is no way to destroy the chip.

Another confusing parameter: on page 16, in Absolute Maximum Ratings table, there is stated: Voltage applied to any pin: -0.3 V to V CC + 0.3 V. So if my VCC = 3.3V minimum voltage is -0.3V and maximum voltage is 3.6V. On the other hand, on page 29 there is table for SD24_A Input Range. From this table we can read that Absolute input voltage range should be between AVSS-1 and AVCC. So if tie digital VCC to analogue AVCC, and digital VSS do analogue AVSS absolute voltages on SD_24 inputs should be from -1V to 3.3V range - which is beyond limits from Absolute Maximum Ratings.

  • Only Absolute Maximum Ratings defines what may cause permanent damage to the device. If you exceed range of other datasheet figures - device may not function according to specification, but it will not become damaged. In case you exceed SD24_A Input Range at give PGA gain, you obviously are not able to measure voltages correctly, ADC output can saturate and basically that's it.

    [edit] SD24_A input range defines linear region of ADC, not necessarily saturation. Note that Specified range at each PGA gain is around 80% of range. Meaning that at VREF=1.2V, PGA=1 and input <500mV, ADC will function according to specs, at input betwee 500mV and 600mV it could be off-specs (of linearity and so on) but output may not be saturated. Only if you exceed 600mV which is 1/2 of VREF in this case, you can expect saturation, but shall not rely to - because saturation conditions are not defined in the specs :) Better just set your limits which are not equal to saturated ADC output. Hope it helps.

  • Thanks for Your answer. It's good to see that my assumptions about SD24 behavior at different gains were correct. I'll move forward with my project :)

    But I'm still a little confused about difference between Absolute Maximum Ratings (-0.3 V to VCC + 0.3 V) and Absolute input voltage range for SD_24 (AVSS - 1V and AVCC). Which one have a precedence?
  • Jakub Rakus said:
    But I'm still a little confused about difference between Absolute Maximum Ratings (-0.3 V to VCC + 0.3 V) and Absolute input voltage range for SD_24 (AVSS - 1V and AVCC). Which one have a precedence?

    It depends. If you exceed Absolute input voltage range for SD_24, you cannot expect correct readings of ADC, yet chip will be fine. If you exceed Absolute Maximum Ratings (-0.3 V to VCC + 0.3 V), you not only risk to get wrong ADC readings but also risk to destroy chip completely or partially.

    Note that below absolute maximum ratings table there's comment: "Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device."

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