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MSP430F4250: SD16_A and clock source

Aswin Prabhu
Prodigy 160 points
Part Number: MSP430F4250

Hello,

While experimenting with SD16_A in MSP430F4250, I noticed that the ADC readings for the same input voltage are different when using different clock sources. Why is it so?

Crystal freq= 4MHz, so ACLK = 4 MHz. FLL+ multiplier is 2, so MCLK=SCLK=8 MHz. Vref = 1.5V. Oversampling ratio= 1024. Unipolar measurement.

a) when ADC clock source is MCLK with divider = 8, ADC clock= 1 MHz. Readings: 0.1426V = 5887, 0.716V = 30869, 1.432V = 62087. Thus y=43642*x - 348.73

b) when ADC clock source is ACLK with divider = 4, ADC clock= 1 MHz. Readings: 0.1426V = 6015, 0.716V = 30992, 1.432V = 62220. Thus y= 43646*x - 223.7

What is the reason for the zero offset on using two different clocks?

  • 0
    Guru 46710 points
    If both ACLK and MCLK is sourced from same clock, then results shall not differ unless your circuit noise changes and ADC difference you see is secondary issue. Take at least 8 samples at each clock/voltage, then compare.
  • 0 in reply to Ilmars
    Prodigy 160 points

    Hello,
    a) 0.1426V sampled by the ADC is sourced from a reference IC through a resistance-divider network. Chances of circuit noise is less.
    b) The readings mentioned is the output of a heavy digital filter: new_value = 0.969*previous_value + 0.031*current_value.
    c) I've checked the readings in both conditions (ACLK & MCLK) at least 10-15 times over the past two days and the values vary from each other by just 2-3 LSB. It is stable.
    d) If the device is put in LPM1 mode (all clocks active, FLL+ loop control disabled), clock source is either MCLK or SCLK and the ADC values are read within an ISR, the results are same as point (b) in the first post, which makes me wonder: What has FLL+ control loop to do with ADC performance?

    In other words, whenever FLL+ control loop is active, I get one set of readings and if either the FLL+ control loop is disabled (LPM1) or ADC is sourced from ACLK directly (FLL+ control loop is not at all in the picture), then I get another set of readings.

  • 0 in reply to Aswin Prabhu
    Guru 46710 points

    Aswin Prabhu said:
    c) I've checked the readings in both conditions (ACLK & MCLK) at least 10-15 times over the past two days and the values vary from each other by just 2-3 LSB. It is stable.

    Not 10..15 times, but 10..15 sequential readings of ADC running in continuous conversion mode. ADC filters need some time to set, first conversion usually is trash. Reference have some settling time either.

    Aswin Prabhu said:
    d) If the device is put in LPM1 mode (all clocks active, FLL+ loop control disabled), clock source is either MCLK or SCLK and the ADC values are read within an ISR, the results are same as point (b) in the first post, which makes me wonder: What has FLL+ control loop to do with ADC performance?

    FLL slightly changes consumption, supply noise and properties of the clock - frequency and jitter, some or all this could possibly influence ADC readings. Try to add some filtering to AVCC - series 10 ohm resistor between DVCC and AVCC bus, and 10nF + 100nF ceramic caps as close to AVCC pin as possible, see if it helps. Also play with delays, especially SD16INTDLYx bits, set it at max. What about reference? Do you have 470nF cap on VREF pin, do you have 100us delay after vref enable?

  • 0 in reply to Ilmars
    Prodigy 160 points
    Hi,
    I resolved the issue sometime back; posting here for those who may face the same issue.
    As mentioned in the first post, the ADC curve had substantial negative offset. Disabling the ADC's high impedance internal buffer made the offset close to zero. The impact of FLL+ control loop was minimal. Main culprit was the buffer.

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