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MSP430F5151: 16MHz crystal as 24MHz clock reference

Part Number: MSP430F5151

Is it possible to use a 16MHz external crystal (connected to XIN/XOUT) as a reference for a 24MHz CPU clock on the F5151?



  • Yes, XT1CLK can be chosen for high-frequency 16 MHz operation (XTS = 1, XT1DRIVE = 2, OSCOFF = XT1BYPASS = XT1OFF = 0) and is selectable as the FLL reference clock source (SELREF = 0) and can then be divided by 16 (FLLREFDIV = 5) and multiplied by 24 (FLLN = 23) to settle the DCO frequency at 24 MHz. Make sure that PMMCOREV is stepped up to 3 level-by-level.


  • Thanks Ryan. What I'm trying to do now is run MCLK at 24MHz (referenced from XT1) and run SMCLK at 16 MHz directly from XT1.

    Here is the code I'm using currently:

        UCSCTL6 &= ~(XT1OFF | XT1BYPASS);               // XT1 On
        UCSCTL6 |= ( XTS + XT1DRIVE_2);                 // Internal load cap
        UCSCTL3 = FLLREFDIV2 + FLLREFDIV0;                                    // FLL Reference Clock = XT1
        UCSCTL4 |= SELM_0;                        // MCLK = X1 (by default)
        UCSCTL2 = 23 + FLLD_1;
        // Loop until XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle
                                                  // Clear XT1,DCO fault flags
          SFRIFG1 &= ~OFIFG;                      // Clear fault flags
        }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

    From this, I'm seeing a 16 MHz MCLK and SMCLK. Can you help me get the MCLK running at 24MHz?



  • Hello Skyler,
    You need to Switch on XT2 by writing 0 in XT2OFF of UCSCTL6 register and check oscillator fault, Set the drive and then select SMCLK and MCLK source properly in UCSCTL4 registers. You can refer below code example:

    UCSCTL6 &= ~XT2OFF; // Set XT2 On
    UCSCTL6 |= XCAP_3; // Internal load cap

    // XT1 is by default on as it is used default reference for the FLL - internal load caps?
    // Loop until XT1,XT2 & DCO stabilizes
    // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG; // Clear fault flags
    }while (SFRIFG1&OFIFG); // Test oscillator fault flag

    UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
    // expected frequency
    UCSCTL4 |= SELA_0 + SELS_5; // Select SMCLK, ACLK source and DCO source

    but this is written for ACLK = LFXT1 = 32768Hz, MCLK = default DCO = 32 x ACLK = 1048576Hz and SMCLK = HF XTAL. You need to change VCore and set proper multiplier for DCO.

    Vikas Chola
  • Skylar,

    I would be surprised if the code shown results in 16 MHz for MCLK and SMCLK. SELS and SELM values are set at 4 by default so UCSCTL4 |= SELM_0 has no effect and you are still referring to the DCOCLKDIV. I'm not sure why you are using FLLD_1 to divide the DCOCLK by 2 but this too is the default setting. DCORSEL should be set to a value of 6 or 7 for 24 MHz operation. Since you must use the FLL control loop at any rate, why not use MSP430F51x2_UCS_10.c and the internal REFO to set MCLK at 24 MHz and run XT1 to source SMCLK for 16 MHz?


    The MSP430F5151 does not have an XT2 module.

  • Thanks Vikas and Ryan.

    The reason for sourcing the MCLK from XT1 is that we need it to be better than 100 ppm over temperature at 24 MHz. Currently, the customer is using a 16 MHz crystal, so we may just replace it with a 24 MHz crystal to make things smoother.


  • Skyler,

    Any solution that sources MCLK through the DCO as controlled by the FLL, sourced either by REFO or XT1, will include frequency temperature drift of 0.1 %/°C. Only MCLK sourced directly from a 24 MHz crystal populated on XT1 will result in better than 100 ppm over temperature. Why does the customer need such precise but different frequencies at both MCLK and SMCLK? Can they use a 24 MHz crystal to directly source MCLK and divide by 2 for a 12 MHz SMCLK?

  • Ryan,

    This is for a Sigfox application, which requires extremely accurate timing of the MCLK and 8 MHz SPI clock (which we are sourcing from SMCLK). We've found that using the internal reference has caused us issues with delays between SPI writing, and affects both the BPSK timing and the spectral mask.

    In our original design, we multiply a 32kHz crystal to run at 24 MHz MCLK and SMCLK and divide the SPI clock by 3, but we wanted to work with what the customer already designed on their board. We'll switch to 24 MHz XT1 for both MCLK and SMCLK, dividing SMCLK by 3 for the SPI clock. Thanks for your help!


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