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MSP430F6733A: maximum system clock when using DCO as a clock source

Part Number: MSP430F6733A

Hi,


lowest voltage and the uart can be clocked upto 460800 baud, with UCOS16 enabled,
since it is exactly one sixteenth of the system clock. All other lower common
baudrates are then also pure integer devisions without a fractional part.

I am a bit in doubt if this is a reliable solution for mass production. The
system clock is provided by the DCO, and the FLL sourced by an external
32768 crystal(+20ppm). The example code at www.ti.com/.../slac693
seems to indicate this is fine, MSP430F673X_UCS_2.c happily sets the system
clock to 8MHz without touching PMMCOREVx registers.

On the otherhand, the datasheet has a note: "The MSP430 CPU is clocked directly
with MCLK. Both the high and low phase of MCLK must not exceed the pulse width
of the specified maximum frequency"

And as mentioned int Table 5-5. DCO Frequency
Duty cycle Measured at SMCLK min: 40%, typ: 50%, max: 60%

So that seems to indicate you need at least to stay away 20% from the maximum
system frequency when using the DCO, and hence a max freq of 6.4Mhz,
contradicting the example, which sets it to 8MHz and disallowing 7372800 Hz.

Is it fine to set the system clock to 7372800 Hz with PMMCOREVx == 0 or can
this occasionally lead to problems?

Regards,

Jeroen
 

  • The DCO always is a suitable clock source for the MCLK (as long as its frequency is below the limit).

    That DCO duty cycle is measured on an external pin, not for an internal connection. Furthermore, the 10% offset is a suspiciously round number. So I'd estimate being 8% below 8 MHz is perfectly safe.

    And if you run the DCO at double the frequency and use DCOCLKDIV, the duty cycle of the original DCO signal does not matter.
  • Yes, you are right. Modulated DCO set at max specified frequency violates "Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency" requirement. I wonder - did anyone notice this before you :)

    Jeroen Hofstee said:
    So that seems to indicate you need at least to stay away 20% from the maximum

    Users guide states:"The five DCO bits divide the DCO range selected by the DCORSEL bits into 32 frequency steps, separated by approximately 8%". It means that at worst case high frequency of the modulator will differ by no more than approximately 8% of the target freq, not 20%. 8% overclocking most likely will not exceed any safety margins of the specs even at whole temperature range. After all TI examples and reference designs uses modulated DCO at max specified CPU frequency w/o hesitation.

    Would be good to get TI msp430 team comment on this.

  • First of all, the fist line is missing in my question, it should have been something like:  "I am using a core clock of 7372800 Hz so the chip can run on its....", sorry about that.

    Anyway, thanks for your reply.

    Clemens Ladisch said:
    That DCO duty cycle is measured on an external pin, not for an internal connection.

    The datasheet states "Duty cycle, Measured at SMCLK", note how, but yes an external pin would be the most straightforward choice and the driver circuit could add additional skewness.

    Clemens Ladisch said:
    Furthermore, the 10% offset is a suspiciously round number. So I'd estimate being 8% below 8 MHz is perfectly safe.

    For completeness, a change from 50% to 40% is 20%, so from that perspective keeping a 8% margin seems small. I do agree with you that it likely fine,
    but not based on the datasheet, but by the fact google doesn't find a single question or answer keeping this skewness into account.

    Clemens Ladisch said:
    And if you run the DCO at double the frequency and use DCOCLKDIV, the duty cycle of the original DCO signal does not matter.

    That is a smart note, for every even divisor the skewness of the input signal doesn't matter at all. Since I am using a divisor of two this this would be perfect. The spec is about the duty cycle measured
    at SMLK though (for which the min / max could deviate much due to the odd divisors). Are you sure the skewness is only caused by the skewness of the original signal and not the DCO its stability?



  • Jeroen Hofstee said:
    Are you sure the skewness is only caused by the skewness of the original signal and not the DCO its stability?

    It's not about skew or stability. Duty cycle of DCO depends on it's operation principle - DCO jumps between two frequencies which differ by approximately 8%, on cycle-by-cycle basis. Obviously it does impact resulting clock duty cycle too. If DCO modulator output is divided by two, duty cycle error also decreases - at worst case CPU will be "overclocked" for some cycles only by approx 4%, not 8%.