lowest voltage and the uart can be clocked upto 460800 baud, with UCOS16 enabled,
since it is exactly one sixteenth of the system clock. All other lower common
baudrates are then also pure integer devisions without a fractional part.
I am a bit in doubt if this is a reliable solution for mass production. The
system clock is provided by the DCO, and the FLL sourced by an external
32768 crystal(+20ppm). The example code at www.ti.com/.../slac693
seems to indicate this is fine, MSP430F673X_UCS_2.c happily sets the system
clock to 8MHz without touching PMMCOREVx registers.
On the otherhand, the datasheet has a note: "The MSP430 CPU is clocked directly
with MCLK. Both the high and low phase of MCLK must not exceed the pulse width
of the specified maximum frequency"
And as mentioned int Table 5-5. DCO Frequency
Duty cycle Measured at SMCLK min: 40%, typ: 50%, max: 60%
So that seems to indicate you need at least to stay away 20% from the maximum
system frequency when using the DCO, and hence a max freq of 6.4Mhz,
contradicting the example, which sets it to 8MHz and disallowing 7372800 Hz.
Is it fine to set the system clock to 7372800 Hz with PMMCOREVx == 0 or can
this occasionally lead to problems?