My customer is using MSP430FR5720 and encountered an issue.
The system suddenly stops working after power cycle and customer found part of code memory is cleared to 0x00.
The issue was observed with 3pcs (in 60pcs total) and address 0xF000 to 0xF58C are cleared to 0x00 after the issue.
This is code area. These 3pcs were re-programmed again, then working fine after that.
Customer is trying to reproduce the issue, but so far no success. So issue probability seems very low.
One problem I found in customer board is that AVCC and DVCC are completely separated on board and power-up timing is like this:
DVCC power-up first, then AVCC power-up after mili-seconds/seconds order.
According to data sheet (SLASE35B), DVCC and AVCC should power-up with same timing.
There is a note at section 5.3.
"(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation."
1) What happens if DVCC and AVCC power-up separately ? Is it likely part of FRAM are cleared to 0x00 ?
2) What can be possible cause of FRAM data clear to 0x00 ?
Thanks and regards,