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MSP430F447: About the FLL problem

Part Number: MSP430F447

Hello.

I am facing following FLL problem in MSP430F447.

However I'm using FLL, DCO frequency is not stable.

For example, when changing the temperature from 25 ° C to -10 ° C, the DCO clock frequency on which FLL is operating changes by 10%.

(I measured SMCLK signal sourced DCO from clock output port.)

The register settings is as follow.

I'm using DCO with FLL at 655.360MHz.

faclk:32.768kHz(crystal)

SCFQCTLN=19
SCFI0=0
FLL_CTL0
0xA3
FLL_CTL1
0x20

SCG0 is always 0.

When I changed to N = 31 in SCFQCTL register and set the frequency of the DCO clock to 1048.576 KHz,

The frequency change by changing temperature disappeared.

This problem has occurred in multiple devices, but it does not occur on all devices.

Is there something wrong with my setting or anything that could cause this problem?

Would you mind trying out if this problem is reproduced in TI too?

Regards,

uchida-k

  • Hello Uchida,

    I think you had a typo up above for I do not think you can set the DCO at 655MHz. Did you mean 655kHz here?
    That being said, our spec for DCO drift over temperature is typical value of -0.3%/°C. With a -35°C shift as you are describing, this means you have 10.5% drift potential. So what you are seeing is within specification of the part.

    To work around this you could perform manual adjustments to DCO at different temperatures (re-calibration).
  • Hi Jace H,

    Thank you for your reply.
    I do not think the DCO frequency will change by 10% while FLL is enable.

    Because in the User Guide, section 5.2.7, it is described that "The error of the effective frequency is zero every 32 DCOCLK cycles and does not accumulate."

    Is my understanding correct?

    As you understand, DCO frequency is 655.36 KHz.

    According to the DCO Frequency Range chapter of the User Guide page 5-11, I understand that the frequency range of the DCO should not be less than 0.65 MHz when all FN_x bits are 0.

    Since the frequency of the DCO you are currently setting is close to 0.65 MHz, will it deviate from this constraint?
    In that case, when all FN_x bits are 0, how much frequencies should be set at minimum?

    Regards,

    uchida-k

  • Hello Uchida-k,

    The section you point to (Section 5.2.7) is speaking on the potential error introduced by mixing two adjacent DCO frequencies. This is zeroed out every 32 clock cycles. However, it does not take in account temperature drift which you are seeing here. As stated before this is within spec of what you would expect for this DCO.

  • Hi Jace H,
    Thank you for your reply.

    I changed the N to 31, that is DCO = 1048.576KHz, then the frequency of DCO did not change when air temperature is changed from 25℃ to -10℃.
    At this frequency, FLL is considered to be working normally.

    Therefore, Is my understanding as follows correct?

    ・the frequency parameter when fdco=2/all FN_x=0/ DCOPLUS = 1 in the table at the page of 48 in the datasheet, is the lowest set value of FLL.

    ・If the frequency set to 0.65MHz increased to 0.75MHz by temperature decrease, FLL cannot reduce to the expected frequency because current FLL set value is minimum.

    ・If the FLL can be set to the expected frequency at any temperature and DCO needs to be set to the lowest frequency, it is necessary to set the DCO frequency to 1.3 MHz.
    (The max frequency value when fdco=2/all FN_x=0/ DCOPLUS = 1 in the datasheet)

    Regards,

    Uchida-k
  • Hello Uchida,

    The FLL portion of the FLL+ module controls the main DCO tap and the modulator to combine two adjacent DCO frequencies. With the temperature drift, these DCO taps can vary by 10% typical. I believe you are right here in that at the lower end, the FLL is set to its lowest values so it cannot mix in lower frequencies to try to compensate for the temperature drift.

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