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MSP430F2410: ADC12 noise using DCO at 4MHz

Part Number: MSP430F2410

Hello,

Posting on behalf of my customer:

I discovered that if I run the ADC12 from the DCO at calibrated 12 MHz, and divide it by 3 (you have register settings to do this) to operate at 4 MHz, the noise and linearity performance is WAY out of spec. I can operate it from other clock settings (including 8 MHz / 2) just fine. I’d like to get to the bottom of it if possible.

Is this expected behavior, and if so, what is the cause?

Thanks,

Keith N.
AFA OH/wPA

  • Hello Keith,

    This is certainly not expected behavior, but I have some further questions.
    What is the source for the ADC Trigger?
    How often is the trigger starting the ADC, aka What is the sampling frequency?
    What is the sample and hold time for the ADC?
    How soon after setting up or changing the DCO/MCLK/SMLCK are samples being taken by the ADC?
  • Here is the setup, I copy-pasted pieces of the code that are relevant so hopefully this is sufficient.

    1K/1000pF RC lowpass on pin 59 of an MSP430F2410TPMR, it's driven by a quiet source in the 200-300 mV area. 2.5V external reference REF5025IDGK with recommended noise reduction caps. TPS71533 regulator driving the whole thing.

    DCO running at 12 MHz, software triggered about once every 50 msec. If the ADC clock source is internal, or DCO/2, or DCO/4, or if I set the DCO to 8 MHz and divide it by 2, then I get expected results. But 12 MHz / 3 produces terrible results. Example data attached.

        BCSCTL1 = CALBC1_12MHZ;  
        DCOCTL = CALDCO_12MHZ;    

        ADC12CTL0 = SHT1_1 + SHT0_1 + ADC12ON;  // 8 clock cycles SH time
        
        // vvv change clock source and divider in this line right here
        ADC12CTL1 = SHP | ADC12DIV_3 | ADC12SSEL_2;    // use 12-MHz MCLK / 4 for clock source and also the sampling timer
        ADC12MCTL0 = SREF_7 + CURRENT_DAC;      // external reference for In Channel 0

    //to trigger a reading from software:

    {

        ADC12CTL0 |= ENC + ADC12SC;      // Sampling and conversion start
        while (ADC12CTL1 & ADC12BUSY); // Keep DCO on for this regardless of whether it's used for the adc clock source
        ADC12CTL0 &= ~ENC;               // Disable ADC conversion
        return ADC12MEM0;
    }

  • Hello Dan,

    For the situation in which you are getting bad results (12MHz/3), can you increase your sample-hold time to see if results improve?
  • I increased the SH time to 64 clock cycles with no difference in performance.
  • Dan,

    I was reviewing your code with a colleague and we noticed that the way you have your divisions setup, you are not getting 4MHz to the ADC. The ADC12DIV_x, where x is a number from 0-7,. This parameter is actually setting the binary number x into the correct portion of the register. For example, ADC12DIV_3 , set the binary number 011 into bit positions 7,6,5 in register ADC12CTL1. Binary 3 corresponds to dividing the clock by a factor 4, not 3. If you want to divide by 3 and get a 4MHz ADC clock form a 12MHz DCO, then you need to use ADC12DIV_2. this may explain some of the discrepancy between your different clock settings and results. I'm not sure how a 3MHz would offer the results you see as well, unless its just hitting a harmonic of your incoming signal or something.
  • Thanks for the input - I think I have been changing the divider but not the comment. But ADC12DIV_3 should divide by 4 to produce 3 MHz, and this solution is working well. I'd rather run faster - but not knowing what's going on here I hope it's safe to stay at 3 MHz.

    The input is DC.
  • Jace, Dan,

    is this behavior still present? If yes were the clocks double checked externally to ensure the ADC really gets the clock we expect?
  • As far as I can tell yes, +/- 40 LSB of noise is the performance we can expect when clocking the ADC12 by dividing the 12-MHz DCO from MCLK by three. I divide by 2 or 4 and it performs as specified. My workaround and solution is to divide by 4 and run the ADC from 3 MHz.

  • Dan,

    is this alwasy true if you use odd divider and does it always work with equal dividers?
    Does the behavior appear on all units or only on some?
    Was this already verified on a TI reference boards or is it only visible on your own PCB?

    Best regards,
    Dietmar
  • Hello Dietmar I did not try dividing by 5 or more. The ADC internal clock works within specified performance also but I wanted the timing to be more certain and the ADC internal clock doesn't have very tight frequency specs. I do not have an eval board, although it does happen on two different designs that we have using the 'F2410. We do not make these in high volume, it is used in fixtures only so now that it is working I'm satisfied with the outcome. Thanks for your help.
  • All,

    is this cased resolved?

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