This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR5969: Using external 16 MHz clock fails

Part Number: MSP430FR5969
Other Parts Discussed in Thread: MSP430FR5994

I'm trying to configure an MSP430FR5969 to use an external 16MHz clock oscillator which drives the HFXIN pin.   However, I am not able to successfully configure the clock system to use this clock.   The clock source seems to default to internal MODCLK (MODOSC), because my timer code sppears to be driven by a 4.8MHz source instead of a 16MHz source.    This failsafe default occurs when a HFXT clock fault occurs that cannot be cleared, as described in the data sheet.    I've probed the PCB and the clock looks stable with no overshoot, 50% duty cycle, etc.   I am looking for suggestions as to what might be wrong.

Here is my code to configure MSP430FR5969 for use of the 16MHz ext. clock:

  *  Init for MSP430FR5969 with 16MHz external oscillator driving the HFXIN pin
 void hfxtClockInit_5MHzClock(void){
     /* set external pins for use as HFXT  */
     PJOUT = 0x00;
     // DS table 6-61, xtal operation is PJSEL1.n=0 PJSEL0.n=1, n=6,7
     PJSEL1 = 0x00;
     PJSEL0 |= BIT6 | BIT7;
     CSCTL0_H = CSKEY >> 8; // Unlock CS registers
     CSCTL1_L = 0b00000000;  // DCO 1Mhz (but DCO not used)
     CSCTL3 = DIVS__1 | DIVM__1; // Set all dividers to 1
     // 16MHz is borderline case for HFFREQ_n bits?, see table 3-1 in SLAU367
     CSCTL4 |= HFFREQ_3 | HFXTBYPASS;      // set clock input freq range
     // check and clear fault regs
       CSCTL5 &= ~(LFXTOFFG | HFXTOFFG);       // Clear XT1 and XT2 fault flag
       SFRIFG1 &= ~OFIFG;
     }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
      CSCTL0_H = 0; // Lock CS registers
  • You have configured ACLK for LFXT, and HFFREQ to "greater than 16 MHz".

    Can you configure P3.4 or PJ.0 to output SMCLK?
  • I am having the exact same issue, any resolution?

  • Hello Wade!

    In the TI Resource Explorer you will find an example code named "msp430fr59xx_cs_04.c" which shows an example of using a crystal on the XT2 HF pins. Please refer to this example code along with section 3.3 of the User's Guide in order to see which commands and registers need to be modified to meet your specific requirements.

    Best regards,

    Matt Calvo

  • I looked at that example... my design uses a MSP430fr5994 with only a 16MHz external clock oscillator.. no 32KHz low freq clock. That example uses a LFXCLK, and sets the DCO to 8MHz. This is not what I'm looking for.

    I want to set all clocks to 16MHz (SMCLK, MCLK), I do not want to use the DCO.

    When I run this code, the clocks are running at 4.8MHz-ish.

    Is there a way to disable the DCO and just tie everything to the external clock oscillator? I

    Here is the clock setup code (that does not work right):

        // Problems setting the external 16MHz clock, this is not working
        // Clock System Setup
        CSCTL0_H = CSKEY >> 8;                  // Unlock CS registers
        CSCTL1_L = 0;                           // ??? DCO not used
        CSCTL2 = SELS__HFXTCLK | SELM__HFXTCLK; // Set SMCLK and MCLK source = HFXT
        CSCTL3 = DIVS__1 | DIVM__1;             // Set all dividers to 1
        CSCTL4 |= HFFREQ_2 | HFXTBYPASS;        // set clock input freq range

        CSCTL5 &= ~(LFXTOFFG | HFXTOFFG);       // Clear XT1 and XT2 fault flag
        SFRIFG1 &= ~OFIFG;
        CSCTL0_H = 0;                           // Lock CS registers

    I am just using the DCO to do development for now, but this is not what I want:

    // DCO code, don't want to use this... external clock init not working

    // Clock System Setup
        CSCTL0_H = CSKEY >> 8;                                                                          // Unlock CS registers
        CSCTL1 = DCORSEL | DCOFSEL_4;                                                       // Set DCO to 16MHz
        CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;                                                // Set all dividers
        CSCTL0_H = 0;                                                                                               // Lock CS registers


  • Wade,

    Yes I understand that your implementation does not match the example code perfectly, it is just a good reference for you to start from. You would just have to remove the code that initializes and implements the LFXTAL and change the sources of the MCLK and SMCLK from the DCO to the HFXTCLK (This is done in the CSCTL2 register).

    For now, I would like you to try and run the example code I suggested, with only removing the Low Frequency Crystal code, and probe P3.4 which is SMCLK sourced by the HFXTAL. Once you ensure that it works properly and see the correct 16MHz signal being output then we can determine why it is not working properly in your implementation.

  • Check the "HFXTOFF" bit of CSCTL4. In fact, I would recommend that you look deeper into every bit of CSCTL4.
  • Wade,

    Mike has a great point, there are bits being set in the example code that you are not setting in your code; and you are also setting some bits that should not be set in regards to CSCTL4. This is the reason why I referred you to the example code as a reference. Regardless of whether you are using an MSP430FR5969 or an MSP430FR5994 there is an HFXTAL example for each that should guide you in correctly initializing high frequency crystal operation.

    Best of luck!

    -Matt Calvo
  • Wade,

    Are there any updates after addressing the issues in the CSCTL4 register?

    Best regards,

    Matt Calvo
  • Wade,

    Please let us know if there are any additional questions you have with this thread so that we can clear them up and log the post accordingly. Thank you for your help!

    Best regards,

    Matt Calvo
  • Wade,

    I am going to go ahead and log this thread since we have not heard back for a while. Thank you for your support and please feel free to make a new post if any other problems should arise!

    Best regards,

    Matt Calvo

**Attention** This is a public forum