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CCS: I WANT TO NEED EXAMPLE CODE OF ADS8332 WITH MSP430....PLZ PLZ HELP ME

Other Parts Discussed in Thread: ADS8332

Tool/software: Code Composer Studio

I WANT TO NEED EXAMPLE CODE OF ADS8332 WITH MSP430....PLZ PLZ HELP ME.......LAST 1 WEEK I TRIED BUT I CAN NOT FIND SOLUTION SO.....PLZ HELP ME

  • The following resources, although not using the exact device requested, demonstrate MSP430 SPI communication with an ADSxx ADC

    e2e.ti.com/.../474562
    www.ti.com/.../430boost-ads1118
    www.ti.com/.../BOOST-ADS7042

    Regards,
    Ryan
  • HI RYAN,

    I HAVE WRITTEN CODE AND WASTE 3 DAYS, BUT CAN NOT READ CFR REGISTER...............HERE IS THE CODE.....

    IS THERE ANY PROB IN SPI INITIALIZATION...........................

    I  HAVE USED 24MHZ CRYSTAL....

    IF U HAVE EXAMPLE CODE THEN SEND ME...................

    IN EMAIL-hitesh.mathukiya@gmail.com

    #include<msp430.h>

    #include"sps_pmm.h"

    #include"sps_clock.h"

    #include"sps_gpio.h"

    //--------------------------------------------------------hitesh--------------------------------------------

    #define         NOP         0x00

    #define         CONV_HIGH        P3OUT |=  BIT6

    #define         CONV_LOW        P3OUT &=~ BIT6

    #define         RESET_HIGH  P3OUT |=  BIT5

    #define         RESET_LOW   P3OUT &=~ BIT5

    #define         CS_LOW      P4OUT &=~ BIT0

    #define         CS_HIGH     P4OUT |=  BIT0

    #define         SCLK        BIT2                              //UCA0CLK

    #define         SDI         BIT0                              //UCA0SIMO

    #define         SDO         BIT1                              //UCA0SOMI

    /*WRITE CFR=1110=E

    SELECT ANALOG CHANNEL=0111=7

    READ CFR=1100=C

    */

    unsigned char SELECT_MANUAL_CHANNEL[4]={0xE2,0XFD}; //MAKE D11=0 FOR MANUAL CHANNNEL       //internal reference=4.096 and range is select vref*1.25=5.12V   so at 5.12V give FFFC and at 0V give 0000

    unsigned char SELECT_AUTO_CHANNEL[4]={0xE2,0XFD};//MAKE D11=1 FOR AUTO CHANNEL

    unsigned char               WRITE_CFR[4]={0xE0,0XAA,0X00,0X00};//WRITE CFR WITH MANUAL CHANNEL

    unsigned char SELECT_ANALOG_CHANNEL[4]={0x72,0XFD};// SELECT ANALOG CHANNEL

    unsigned char READ_CFR[8]={0xC0,0X00,0X00,0X00};// READ CFR

    unsigned char CHANNEL_0[4]={0X02,0XFD};// SELECT CHANNEL0

    unsigned char CHANNEL_1[4]={0X12,0XFD};// SELECT CHANNEL1

    unsigned char CHANNEL_2[4]={0X22,0XFD};// SELECT CHANNEL2

    unsigned char CHANNEL_3[4]={0X32,0XFD};// SELECT CHANNEL3

    unsigned char CHANNEL_4[4]={0X42,0XFD};// SELECT CHANNEL4

    unsigned char CHANNEL_5[4]={0X52,0XFD};// SELECT CHANNEL5

    unsigned char CHANNEL_6[4]={0X62,0XFD};// SELECT CHANNEL6

    unsigned char CHANNEL_7[4]={0X72,0XFD};// SELECT CHANNEL7

    unsigned char rec;

    unsigned char response_buffer1[300];

    unsigned char j=0,xoo,data_comin=0,jj=0;

    unsigned int iii=0;

    unsigned char byte[5],pin_init=1;

    unsigned char flag=0;

    unsigned char nop_flag=0;

    unsigned int next_data[11];

    float con_data;

    long next_data1;

    long avg_data=0;

    unsigned int adc_data1,final_data=0;

    unsigned char data_hitesh[5];

    unsigned int count,n;

    unsigned char all_channel=1;

    unsigned char send_all_data=0,data_is_receive=0,send_one_data=0,not_send_data=0,channel=0,select_mux_4067=0,select_mux_4067_flag=0,switch_all_channel=1;

    unsigned char enigma=0;

    unsigned int   get_get=0;

    unsigned char response_buffer2[50];

    unsigned int next_inc=0;

    void reset();

    void round_off_the_bit();

    void nop();

    void write_RANGE_SEL_REG_Register1();

    void transfer_frame(unsigned char frame_data);

    void spi_init();

    void con_all_channel();

    void get_data(unsigned int hh);

    void pheonix_execute_default_ip_sequence();

    //-----------------------------hitesh---------------------------------------------------------------------------------

    //____________________________________________________________CLOCK RELATED FUNCTIONS

    void pheonix_set_pmm_level_for_24_mhz();

    void pheonix_initialize_the_clock();

    //____________________________________________________________CLOCK RELATED VARIABLES

    bool bReturn = STATUS_FAIL;

    int main(void)

    {

       WDTCTL = WDTPW | WDTHOLD;   // Stop watchdog timer

       pheonix_initalize_all_gpio_ports();

       pheonix_set_pmm_level_for_24_mhz();

       pheonix_initialize_the_clock();

       //------------------- SPI-----------------------------------------------------------

       spi_init();

       reset();

       write_RANGE_SEL_REG_Register1();

       //-----------------hitesh-------------------------------------------------------------

       __bis_SR_register(GIE);

       while (1)

       {

                  for(i=0;i<=3;i++){

                      transfer_frame(WRITE_CFR[i]);

                  }

            for(i=0;i<=1;i++){

                transfer_frame(READ_CFR[i]);

            }

       }

    }

    void reset(){

    //   RESET_HIGH;

       CS_LOW;

           RESET_LOW;

             __delay_cycles(10000);

             //RESET_LOW;

              RESET_HIGH;

              __delay_cycles(20000);

             // RESET_HIGH;

              CS_HIGH;

    }

    //__________________________________________________________________CLOCK_________________________________________________________________

    void pheonix_set_pmm_level_for_24_mhz()

    {

       pheonix_set_v_core_to_level(PMM_CORE_LEVEL_1);

       __delay_cycles(100000);

       pheonix_set_v_core_to_level( PMM_CORE_LEVEL_2);

       __delay_cycles(100000);

       pheonix_set_v_core_to_level( PMM_CORE_LEVEL_3);

       __delay_cycles(100000);

    }

    void pheonix_initialize_the_clock()

    {

       UCS_setExternalClockSource(32768, 24000000); // XT1CLK input,// XT2CLK input

       UCS_turnOffXT1();

       bReturn = STATUS_FAIL;

       do

       {

           bReturn = UCS_turnOnXT2WithTimeout(UCS_XT2_DRIVE_24MHZ_32MHZ, 50000);

           __delay_cycles(50000);

       }

       while (!bReturn);

       if (bReturn == STATUS_FAIL)

       {

           while (1);

       }

       UCS_initClockSignal(UCS_ACLK, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1);

       UCS_initClockSignal(UCS_MCLK, UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_1);

       UCS_initClockSignal(UCS_SMCLK, UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_1);

    }

    //___________________________________________hitesh____________________________________________________

    //-------------------------------------------------------------------------------------------------------

    void spi_init(){

       UCB0CTL1 |= UCSWRST;                      // **Put state machine in reset**

       UCB0CTL0 |= UCMST+UCSYNC+UCMODE_1+UCMSB+UCCKPL;    // 3-pin, 8-bit SPI master    UCCKPL+

       UCB0CTL0 &= ~(UC7BIT+UCPEN+UCCKPH);                   //gettinng device id proper

       // Clock polarity high, MSB

       UCB0CTL1 |= UCSSEL_1;                     // SMCLK

       UCB0BR0 = 0x02;                           // /2

       UCB0BR1 = 0;                              //

       UCB0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**

       //UCA0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt

    }

    void nop()

    {

       nop_flag=1;

       int i=0;

     //  CS_LOW;

       for(i=0;i<=3;i++){

           transfer_frame(NOP);

       }

      // CS_HIGH;

       nop_flag=0;

       //RESET_HIGH;

       //  RESET_LOW;

    }

    void write_RANGE_SEL_REG_Register1()

    {

       int i=0;

      //    RESET_HIGH;

      // RESET_LOW;

       //   __delay_cycles(10000);

        //   RESET_HIGH;

      // CS_HIGH;

       for(i=0;i<=8;i++){

           transfer_frame(READ_CFR[i]);

       }

       //nop();

       i=0;

    //   CS_LOW;

       CS_LOW;

       for(i=0;i<=3;i++){

           transfer_frame(WRITE_CFR[i]);

       }

       i=0;

       CS_HIGH;

       CS_LOW;

       for(i=0;i<=4;i++){

           transfer_frame(READ_CFR[i]);

       }

       //nop();

       i=0;

       CS_HIGH;

       CS_LOW;

       for(i=0;i<=3;i++){

           transfer_frame(SELECT_MANUAL_CHANNEL[i]);

       }

       i=0;

       CS_HIGH;

       CS_LOW;

       for(i=0;i<=3;i++){

           transfer_frame(WRITE_CFR[i]);

       }

       i=0;

       CS_HIGH;

       CS_LOW;

       for(i=0;i<=3;i++){

           transfer_frame(SELECT_ANALOG_CHANNEL[i]);

       }

       i=0;

       CS_HIGH;

       CS_LOW;

       for(i=0;i<=3;i++){

           transfer_frame(READ_CFR[i]);

       }

       i=0;

       nop();

       CS_HIGH;

       CS_LOW;

       for(i=0;i<=3;i++){

           transfer_frame(CHANNEL_3[i]);

       }

       i=0;

       CS_HIGH;

    }

    void transfer_frame(unsigned char frame_data){

       while(!(UCB0IFG & UCTXIFG));

       UCB0TXBUF=frame_data;   //P3.3

       while(!(UCB0IFG & UCRXIFG));

       rec=UCB0RXBUF;

       //byte[iii] = UCB0RXBUF;  // P3.4

       iii++;

       if(iii>1){

           iii=0;

           next_data[j]=(int)((byte[1] << 0) & 0xFF) + ((byte[0] << 8) & 0xFFFF);

           avg_data=next_data[j]+avg_data;

           j++;

           if(j>5){

               final_data=avg_data/6;  ///AVERAGING WITH 6 DATA

               j=0;

               avg_data=0;

               count++;

               enigma=1;

           }

           next_data1=(((long)final_data)*4300);   //4.3*DATA=6.144  4.3 REFERANCE VOLT

           con_data=(float)((next_data1)/0XFFFF);   //devide by=FFFC

           adc_data1=con_data;

           //data[3] = ((adc_data1 % 10))+0x30;

           data_hitesh[0] = (adc_data1 / 10000)+0x30;    //making decimal to asci    5 asci value 0x35

           data_hitesh[1] = ((adc_data1 % 10000)/1000)+0x30;    //making decimal to asci    5 hex value 0x35

           data_hitesh[2] = ((adc_data1 % 1000) / 100)+0x30;

           data_hitesh[3] = ((adc_data1 % 100) / 10)+0x30;

           data_hitesh[4] = ((adc_data1 % 10))+0x30;

       }

    }

    void get_data(unsigned int hh)

    {

       /*unsigned char lexi_1,lexi_2;

       lexi_1=(all_channel/10)+0x30;

       lexi_2=(all_channel%10)+0x30;*/

       response_buffer1[hh]=data_hitesh[0];

       response_buffer1[hh+1]=data_hitesh[1];

       response_buffer1[hh+2]='.';

       //response_buffer1[hh+2]=;

       response_buffer1[hh+3]=data_hitesh[2];

       response_buffer1[hh+4]=data_hitesh[3];

       response_buffer1[hh+5]=',';

    }

  • Hi Hitesh,

    What MSP430 device derivative are you using and what is the specific issue you are experiencing? Can you provide oscilloscope or logic analyzer screenshots of the communication? If clock polarity is high then it appears that the data should be captured on the first UCLK edge (UCCKPH set). UCSSEL_1 is also ACLK source select, not SMCLK. I do not see where you initizliaze the GPIO for SPI functionality (set P3SEL.x bits).

    Regards,
    Ryan
  • This thread is being closed due to inactivity.

    Ryan

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