msp430fr5849: Clock Tree to generate a 50khz interrupt

Blake Carpenter

Part Number: MSP430FR5849

Hi MCU Support,

My customer is working with a FR5849 with 2 UARTs and trying to get a slow interrupt at once a second type rates. He writes:

For this MCU, I am seeing that the ACLK limitation is 50KHz, but it has the option to be sourced from the DCO and has a maximum divider of 32. I can’t seem to get it down to 50KHz even if I run the DCO at a bare minimum of 2.7MHz. I’d rather not use an external crystal for the Lo Frequency source and there does not appear to be any other options.

When asked why, he further writes:

I am trying to form a clock tree. The 50K was just the limitation shown in the data sheet. After further consideration, it appears that the DCO is not able to drive the ACLK module at all, so it is now a moot point. Looks like the only option to use ACLK is from the external LF osc module that needs a clock crystal. I am not going to go that route.

So, I am just looking at other ways to generate a 1 second or so interrupt from the SMCLK and a Timer or two. I think I can get both my UARTS running from a 2MHz SMCLK in oversampling mode. I need 9.6K and 57.6K BAUDs.

One of the UARTs is in listen mode always and responds to the host UART. (9.6K)
The other UART should probably get an update from it about once a second or perhaps a little longer. So, I need a slow interrupt to trigger that routine. I was going to derive that time interval from ACLK, but now I’ll have to derive the timer from SMCLK, which needs to be 2MHz. I wanted to avoid using a software timer, so perhaps I can gang two timers together to get what I need and avoid hitting the CPU except when I need to service the 2nd 1 second update UART.

Then Finally:

Am I able to the take the TA0 Timer Clock signal (after dividing SMCLK by 64) and feeding that to TA1 as a clock source? I’m having a hard time seeing how that works through the I/O logic diagram. I don’t see any timer inputs/outputs. Does P1IN.x feed to TA1CLK input?

I am hoping to go from SMCLK = 2MHz /1 to 8 / 1 to 8 / 1 to 8 / 1 to 8/ 1 to 65,535 = some very low value of Hz as an interrupt.

My first thought was perhaps the WDT... Any thoughts on his course of action?

Best Regards,

Blake

over 6 years ago

0 Jeff Hastings over 6 years ago

Intellectual 820 points

yes, you can 'gang' or 'daisy-chain' timers, but an external pin interconnection will perhaps be required.
configure the first timer for a rectangle/square wave output and use that to clock the second channel.

There might be other possible approaches. I'm not an expert on the fr5849 per se, but have used this technique for other makes/families of MCU.

Yes, P1.1 will be TA1CLK if you configure the pin for such operation. see SLASE34 table 6-48.

0 Caleb Overbay over 6 years ago

TI__Genius 15370 points

Hi Blake,

The goal is to generate an interrupt at ~1 second intervals so I don't understand the attempts to chain timers together. There are three ways I can imagine doing this.

Source ACLK from the VLO and then use this as the source to a timer
1. The VLO in this part typically oscillates at 9.4kHz and has a wide range of variability
2. You can achieve greater accuracy with the VLO using the techniques described in Using the VLO Library
Use the WDT in interval mode
1. Source from either SMCLK or the VLO
2. The dividers are a less flexible than for a timer
Use a timer source from SMCLK at 2MHz
1. You can divide SMCLK by 64 using timerA
  1. 2MHz/64 = 31.25kHz
2. Then set CCR0 of the timer to 31250 to achieve a 1 second interval