MSP430F123: State of RESET line during fuse check

Some more questions about JTAG...

I'm looking at a scope trace of the fuse check and my FET tool does 8 strobes of the TCK line, a one TCK cycle delay, then two strobes of the TMS line,  then two more strobes of the TCK line. This is nearly identical to

SLAA149 states: "When initializing JTAG access after power-up, a fuse check must be done before JTAG access is granted. Toggling of the TMS signal twice performs the check. It is recommended that a minimum of six TCK clocks be sent to the target device while TMS is high followed by setting TMS low for at least one TCK clock. This sets the JTAG state machine (TAP controller) to a defined starting point: the Run-Test/Idle state. This procedure can also be used at any time during JTAG communication to reset the JTAG port."

However SLAU320ab states:  When initializing JTAG access after power up, a fuse check must be done before JTAG access is granted. Toggling of the TMS signal twice performs the check."  So they both agree on two strobes, but fig 1-13 in SLAU320ab  has 3 strobes of TMS showing the fuse is checked on the 3rd strobe.

So what's right?

Also, SLAU320 LAU320ab states: "Under certain circumstances (for example, plugging in a battery), a toggling of TMS may accidentally occur while TDI is logical low. In that case, no current flows through the security fuse, but the internal logic remembers that a fuse check was performed. Thus, the fuse is mistakenly recognized as programmed (that is, blown). To avoid the issue, newer MSP430 JTAG implementations (devices with CPUXv2 - see Table 1-15) also reset the internal fuse-check logic on performing a reset of the TAP controller. Thus, it is recommended to first perform a reset of the TAP and then check the JTAG fuse status..."

This creates two conflicting figures, fig 5 in SLAU149 and fig 1-13 in SLAU320 about when to reset the TAP controller. 

So what's is right?

Finally, from SLAU320: "Following the same sequence in SBW mode has the side effect of changing the TAP controller state while the fuse check is performed. As described in Section 1.2.3.1, the internal signal TCK is generated automatically in every TDI_SLOT. Performing a fuse check in SBW mode, starting directly after a reset of the TAP controller, ends in its Exit2-DR state. Two more dummy TCK cycles must be generated to return to Run-Test/Idle state; one TCK with SBWTDIO being high during the TMS_SLOT followed by one TCK with SBWTDIO being low during the TMS_SLOT (reference function: ResetTAP_sbw)." but are two strobes after the fuse test only necessary in SBW mode and would there be any effect of the two two strobes in 4-wire jtag mode (as it appeary my FET tool is doing)?

Thanks in advance,