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MSP430F5508: USCI UCBUSY bit behavior

Part Number: MSP430F5508

Hello. Unfortunately, neither in the datasheet nor in the user guide not found the time chart regarding the reset bit USBUSY. What is meant of words "USCI is inactive" in user guide Table 37-20? Experimentally I get that for UCCKPH = 1 and UCCKPL =0, USBUSY reset immediately after the last rising edge. I.e., UNTIL last falling edge. I.e. during USCI still active. As it should be or is this bug?

  • Looking at figure 37-4 in the User's Guide, that rising edge is the last RX sample point, i.e., the last time where anything happens in the TX/RX state machine. The following falling edge is done only to return the clock signal to its idle state, which, apparently, does not count as "active". It looks as if the UCBUSY behaviour is intended.

    (I haven't done any experiments, but I'd guess that UCBUSY gets set when the first TX bit is shifted out, which is one half bit before the first clock edge.)

    In any case, even if this were a bug, it would not change the fact that this is the actual behaviour of the chip that you have to work with. ;-)
  • Thank you very much for the reply. I agree that most likely implements this logic. However, I'm trying to find official confirmation. If figure 37-4 depicts the behavior of this bit would be no issue at all. Without confirmation there is a risk of changing the behavior of the MCU in the future without any notification:(
  • Hello Alexei,

    UCBUSY logic is as described by Clemens and there are no UCBUSY errata present in SPI mode for this device.