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MSP430G2210: How to implement 12bit/1ksps slope ADC using Comparator A+.

Part Number: MSP430G2210

Hello Champs,
My customer is looking for an application note or example how to implement a 12bit/1ksps slope ADC with voltage input using Comparator A+. Sofar I shared www.ti.com/.../slaa129b.pdf but the resolution is only 6 bit where 12 bits is required( minimum 10 bits)

(next i shared www.ti.com/.../slaa806.pdf, http://www.ti.com/lit/SLAA803, www.ti.com/.../swab003a.pdf)

Customer is open to any suggestion convert voltage@ 12bit/1ksps at lowest price

Thanks,

Best regards, Patrick
EP-FAE

  • Hello Patrick,

    The resources you pointed to are the best we have for slope ADC. In addition you can check out the following application note about ADC oversampling that can potentially be used on the value line FRAM parts. (http://www.ti.com/lit/slaa694 ) I'm unsure how big the code is for doing the oversampling as that aspect is not covered in the application note. But this method can improve the 10bit ADC to 12 bit potentially. It does slow down the capture rate as you have to take more samples to filter out noise.
  • Hello Patrick,

    Just spoke with one of the Oversampling app note authors. Its un-optimized (the included code) and is running around 12kB FRAM if you take out the UART coms and external DAC controls. Its mostly due tot he MATH library being included. I can see some room for optimization, but probably not to the levels of the value line FRAM platform (4kB or less).