MSP430F5171: Unified Clock System module problem

Pawel Mag

Part Number: MSP430F5171

Hi,

I have a problem with Unified Clock System module. When I wake-up MCU form low power state sometimes FLL loop can't catch correct frequency and DCOFFG flag in UCSCTL7 register is set. This is probably caused by incorrect DCO and MOD settings in register UCSCTL0 (value is 0x00F8). I turn on interrupt from UCS module and in ISR reset DCOFFG flag but nothing happends. UCSCTL0 value is still 0x00F8 and NMI interrup hang entire device. This error is very rarely and occurs only when device is switched from battery to main power by relay.

I created shapshot of all MCU registers when this occured.

5165.registers.txt

521177 81
R PC 0x00000011 0x00BD8C
R SP 0x00000011 0x0023EE
R SR 0x0000000B 0x0000
R R3 0x00000011 0x000000
R R4 0x00000011 0x00FFFF
R R5 0x00000011 0x000000
R R6 0x00000011 0x000000
R R7 0x00000011 0x000001
R R8 0x00000011 0x001C02
R R9 0x00000011 0x001E16
R R10 0x00000011 0x000000
R R11 0x00000011 0x000001
R R12 0x00000011 0x000000
R R13 0x00000011 0x000000
R R14 0x00000011 0x000000
R R15 0x00000011 0x000203
R Comparator_B_CBCTL0 0x0000000B 0x008C
R Comparator_B_CBCTL1 0x0000000B 0x1609
R Comparator_B_CBCTL2 0x0000000B 0x37B3
R Comparator_B_CBCTL3 0x0000000B 0x7000
R Comparator_B_CBINT 0x0000000B 0x0102
R Comparator_B_CBIV 0x0000000B 0x0000
R CRC16_CRCDI 0x0000000B 0x0000
R CRC16_CRCDIRB 0x0000000B 0x0000
R CRC16_CRCINIRES 0x0000000B 0xFFFF
R CRC16_CRCRESR 0x0000000B 0xFFFF
R DMA_DMACTL0 0x0000000B 0x0000
R DMA_DMACTL1 0x0000000B 0x0000
R DMA_DMACTL2 0x0000000B 0x0000
R DMA_DMACTL3 0x0000000B 0x0000
R DMA_DMACTL4 0x0000000B 0x0000
R DMA_DMAIV 0x0000000B 0x0000
R DMA_DMA0CTL 0x0000000B 0x0000
R DMA_DMA0SA 0x0000001B 0x00000000
R DMA_DMA0DA 0x0000001B 0x00001000
R DMA_DMA0SZ 0x0000000B 0x0620
R DMA_DMA1CTL 0x0000000B 0x0000
R DMA_DMA1SA 0x0000001B 0x00000000
R DMA_DMA1DA 0x0000001B 0x00000000
R DMA_DMA1SZ 0x0000000B 0x0040
R DMA_DMA2CTL 0x0000000B 0x0000
R DMA_DMA2SA 0x0000001B 0x00000100
R DMA_DMA2DA 0x0000001B 0x00000004
R DMA_DMA2SZ 0x0000000B 0x0010
R Flash_FCTL1 0x0000000B 0x9600
R Flash_FCTL3 0x0000000B 0x9658
R Flash_FCTL4 0x0000000B 0x9600
R MPY_16__Multiplier__16_Bit_Mode_MPY 0x0000000B 0x0002
R MPY_16__Multiplier__16_Bit_Mode_MPYS 0x0000000B 0x0002
R MPY_16__Multiplier__16_Bit_Mode_MAC 0x0000000B 0x0002
R MPY_16__Multiplier__16_Bit_Mode_MACS 0x0000000B 0x0002
R MPY_16__Multiplier__16_Bit_Mode_OP2 0x0000000B 0x001A
R MPY_16__Multiplier__16_Bit_Mode_RESLO 0x0000000B 0x0034
R MPY_16__Multiplier__16_Bit_Mode_RESHI 0x0000000B 0x0000
R MPY_16__Multiplier__16_Bit_Mode_SUMEXT 0x0000000B 0x0000
R MPY_16__Multiplier__16_Bit_Mode_MPY32CTL0 0x0000000B 0x0000
R MPY_32__Multiplier__32_Bit_Mode_MPY32L 0x0000000B 0x0002
R MPY_32__Multiplier__32_Bit_Mode_MPY32H 0x0000000B 0x0000
R MPY_32__Multiplier__32_Bit_Mode_MPYS32L 0x0000000B 0x0002
R MPY_32__Multiplier__32_Bit_Mode_MPYS32H 0x0000000B 0x0000
R MPY_32__Multiplier__32_Bit_Mode_MAC32L 0x0000000B 0x0002
R MPY_32__Multiplier__32_Bit_Mode_MAC32H 0x0000000B 0x0000
R MPY_32__Multiplier__32_Bit_Mode_MACS32L 0x0000000B 0x0002
R MPY_32__Multiplier__32_Bit_Mode_MACS32H 0x0000000B 0x0000
R MPY_32__Multiplier__32_Bit_Mode_OP2L 0x0000000B 0x001A
R MPY_32__Multiplier__32_Bit_Mode_OP2H 0x0000000B 0x05F5
R MPY_32__Multiplier__32_Bit_Mode_RES0 0x0000000B 0x0034
R MPY_32__Multiplier__32_Bit_Mode_RES1 0x0000000B 0x0000
R MPY_32__Multiplier__32_Bit_Mode_RES2 0x0000000B 0x0000
R MPY_32__Multiplier__32_Bit_Mode_RES3 0x0000000B 0x0000
R Port_A_PAIN 0x0000000B 0xF0F6
R Port_A_PAOUT 0x0000000B 0x3000
R Port_A_PADIR 0x0000000B 0x3F09
R Port_A_PAREN 0x0000000B 0x0000
R Port_A_PADS 0x0000000B 0x0000
R Port_A_PASEL 0x0000000B 0x0006
R Port_A_PAIES 0x0000000B 0x8050
R Port_A_PAIE 0x0000000B 0xC0B0
R Port_A_PAIFG 0x0000000B 0xE3F2
R Port_1_2_P1IN 0x0000000D 0xF6
R Port_1_2_P1OUT 0x0000000D 0x00
R Port_1_2_P1DIR 0x0000000D 0x09
R Port_1_2_P1REN 0x0000000D 0x00
R Port_1_2_P1DS 0x0000000D 0x00
R Port_1_2_P1SEL 0x0000000D 0x06
R Port_1_2_P1IV 0x0000000B 0x000A
R Port_1_2_P1IES 0x0000000D 0x50
R Port_1_2_P1IE 0x0000000D 0xB0
R Port_1_2_P1IFG 0x0000000D 0xF2
R Port_1_2_P2IN 0x0000000D 0xF0
R Port_1_2_P2OUT 0x0000000D 0x30
R Port_1_2_P2DIR 0x0000000D 0x3F
R Port_1_2_P2REN 0x0000000D 0x00
R Port_1_2_P2DS 0x0000000D 0x00
R Port_1_2_P2SEL 0x0000000D 0x00
R Port_1_2_P2IV 0x0000000B 0x000E
R Port_1_2_P2IES 0x0000000D 0x80
R Port_1_2_P2IE 0x0000000D 0xC0
R Port_1_2_P2IFG 0x0000000D 0xE3
R Port_B_PBIN 0x0000000B 0x00C0
R Port_B_PBOUT 0x0000000B 0x0000
R Port_B_PBDIR 0x0000000B 0x0013
R Port_B_PBREN 0x0000000B 0x0000
R Port_B_PBDS 0x0000000B 0x0000
R Port_B_PBSEL 0x0000000B 0x0000
R Port_3_P3IN 0x0000000D 0xC0
R Port_3_P3OUT 0x0000000D 0x00
R Port_3_P3DIR 0x0000000D 0x13
R Port_3_P3REN 0x0000000D 0x00
R Port_3_P3DS 0x0000000D 0x00
R Port_3_P3SEL 0x0000000D 0x00
R Port_J_PJIN 0x0000000B 0x0040
R Port_J_PJOUT 0x0000000B 0x0000
R Port_J_PJDIR 0x0000000B 0x0000
R Port_J_PJREN 0x0000000B 0x0000
R Port_J_PJDS 0x0000000B 0x0000
R Port_J_PJSEL 0x0000000B 0x0030
R Port_Mapping_Control_PMAPKEYID 0x0000000B 0x96A5
R Port_Mapping_Control_PMAPCTL 0x0000000B 0x0001
R Port_Mapping_Port_1_P1MAP01 0x0000000B 0x0201
R Port_Mapping_Port_1_P1MAP23 0x0000000B 0x0604
R Port_Mapping_Port_1_P1MAP45 0x0000000B 0x0305
R Port_Mapping_Port_1_P1MAP67 0x0000000B 0x0807
R Port_Mapping_Port_1_P1MAP0 0x0000000D 0x01
R Port_Mapping_Port_1_P1MAP1 0x0000000D 0x02
R Port_Mapping_Port_1_P1MAP2 0x0000000D 0x04
R Port_Mapping_Port_1_P1MAP3 0x0000000D 0x06
R Port_Mapping_Port_1_P1MAP4 0x0000000D 0x05
R Port_Mapping_Port_1_P1MAP5 0x0000000D 0x03
R Port_Mapping_Port_1_P1MAP6 0x0000000D 0x07
R Port_Mapping_Port_1_P1MAP7 0x0000000D 0x08
R Port_Mapping_Port_2_P2MAP01 0x0000000B 0x0A09
R Port_Mapping_Port_2_P2MAP23 0x0000000B 0x0C0B
R Port_Mapping_Port_2_P2MAP45 0x0000000B 0x0E0D
R Port_Mapping_Port_2_P2MAP67 0x0000000B 0x100F
R Port_Mapping_Port_2_P2MAP0 0x0000000D 0x09
R Port_Mapping_Port_2_P2MAP1 0x0000000D 0x0A
R Port_Mapping_Port_2_P2MAP2 0x0000000D 0x0B
R Port_Mapping_Port_2_P2MAP3 0x0000000D 0x0C
R Port_Mapping_Port_2_P2MAP4 0x0000000D 0x0D
R Port_Mapping_Port_2_P2MAP5 0x0000000D 0x0E
R Port_Mapping_Port_2_P2MAP6 0x0000000D 0x0F
R Port_Mapping_Port_2_P2MAP7 0x0000000D 0x10
R Port_Mapping_Port_3_P3MAP01 0x0000000B 0x1211
R Port_Mapping_Port_3_P3MAP23 0x0000000B 0x1413
R Port_Mapping_Port_3_P3MAP45 0x0000000B 0x1815
R Port_Mapping_Port_3_P3MAP67 0x0000000B 0x1617
R Port_Mapping_Port_3_P3MAP0 0x0000000D 0x11
R Port_Mapping_Port_3_P3MAP1 0x0000000D 0x12
R Port_Mapping_Port_3_P3MAP2 0x0000000D 0x13
R Port_Mapping_Port_3_P3MAP3 0x0000000D 0x14
R Port_Mapping_Port_3_P3MAP4 0x0000000D 0x15
R Port_Mapping_Port_3_P3MAP5 0x0000000D 0x18
R Port_Mapping_Port_3_P3MAP6 0x0000000D 0x17
R Port_Mapping_Port_3_P3MAP7 0x0000000D 0x16
R PMM__Power_Management_System_PMMCTL0 0x0000000B 0x9602
R PMM__Power_Management_System_PMMCTL1 0x0000000B 0x0000
R PMM__Power_Management_System_SVSMHCTL 0x0000000B 0x4602
R PMM__Power_Management_System_SVSMLCTL 0x0000000B 0x4602
R PMM__Power_Management_System_SVSMIO 0x0000000B 0x0020
R PMM__Power_Management_System_PMMIFG 0x0000000B 0x0011
R PMM__Power_Management_System_PMMRIE 0x0000000B 0x1100
R PMM__Power_Management_System_PM5CTL0 0x0000000B 0x0000
R RC__RAM_Control_Module_RCCTL0 0x0000000B 0x6900
R Shared_Reference_REFCTL0 0x0000000B 0x0280
R SFR__Special_Function_Registers_SFRIE1 0x0000000B 0x0002
R SFR__Special_Function_Registers_SFRIFG1 0x0000000B 0x0082
R SFR__Special_Function_Registers_SFRRPCR 0x0000000B 0x000D
R SYS__System_Module_SYSCTL 0x0000000B 0x0000
R SYS__System_Module_SYSBSLC 0x0000000B 0x8003
R SYS__System_Module_SYSJMBC 0x0000000B 0x000C
R SYS__System_Module_SYSJMBI0 0x0000000B 0x0000
R SYS__System_Module_SYSJMBI1 0x0000000B 0x0000
R SYS__System_Module_SYSJMBO0 0x0000000B 0x0000
R SYS__System_Module_SYSJMBO1 0x0000000B 0x0000
R SYS__System_Module_SYSBERRIV 0x0000000B 0x3FFF
R SYS__System_Module_SYSUNIV 0x0000000B 0x0004
R SYS__System_Module_SYSSNIV 0x0000000B 0x0000
R SYS__System_Module_SYSRSTIV 0x0000000B 0x0000
R Timer0_A3_TA0CTL 0x0000000B 0x0111
R Timer0_A3_TA0CCTL0 0x0000000B 0x0011
R Timer0_A3_TA0CCTL1 0x0000000B 0x0001
R Timer0_A3_TA0CCTL2 0x0000000B 0x0001
R Timer0_A3_TA0R 0x0000000B 0x21DE
R Timer0_A3_TA0CCR0 0x0000000B 0x4000
R Timer0_A3_TA0CCR1 0x0000000B 0x0000
R Timer0_A3_TA0CCR2 0x0000000B 0x0000
R Timer0_A3_TA0IV 0x0000000B 0x0000
R Timer0_A3_TA0EX0 0x0000000B 0x0000
R Timer0_D3_TD0CTL0 0x0000000B 0x02C1
R Timer0_D3_TD0CTL1 0x0000000B 0x0700
R Timer0_D3_TD0CTL2 0x0000000B 0x0000
R Timer0_D3_TD0R 0x0000000B 0x2E57
R Timer0_D3_TD0CCTL0 0x0000000B 0x0000
R Timer0_D3_TD0CCR0 0x0000000B 0x493E
R Timer0_D3_TD0CL0 0x0000000B 0x493E
R Timer0_D3_TD0CCTL1 0x0000000B 0x0001
R Timer0_D3_TD0CCR1 0x0000000B 0x0000
R Timer0_D3_TD0CL1 0x0000000B 0x0000
R Timer0_D3_TD0CCTL2 0x0000000B 0x0001
R Timer0_D3_TD0CCR2 0x0000000B 0x0000
R Timer0_D3_TD0CL2 0x0000000B 0x0000
R Timer0_D3_TD0HCTL0 0x0000000B 0x0000
R Timer0_D3_TD0HCTL1 0x0000000B 0x0080
R Timer0_D3_TD0HINT 0x0000000B 0x0000
R Timer0_D3_TD0IV 0x0000000B 0x0000
R Timer1_D3_TD1CTL0 0x0000000B 0x0000
R Timer1_D3_TD1CTL1 0x0000000B 0x0000
R Timer1_D3_TD1CTL2 0x0000000B 0x0000
R Timer1_D3_TD1R 0x0000000B 0x0000
R Timer1_D3_TD1CCTL0 0x0000000B 0x0000
R Timer1_D3_TD1CCR0 0x0000000B 0x0000
R Timer1_D3_TD1CL0 0x0000000B 0x0000
R Timer1_D3_TD1CCTL1 0x0000000B 0x0000
R Timer1_D3_TD1CCR1 0x0000000B 0x0000
R Timer1_D3_TD1CL1 0x0000000B 0x0000
R Timer1_D3_TD1CCTL2 0x0000000B 0x0000
R Timer1_D3_TD1CCR2 0x0000000B 0x0000
R Timer1_D3_TD1CL2 0x0000000B 0x0000
R Timer1_D3_TD1HCTL0 0x0000000B 0x0000
R Timer1_D3_TD1HCTL1 0x0000000B 0x0080
R Timer1_D3_TD1HINT 0x0000000B 0x0000
R Timer1_D3_TD1IV 0x0000000B 0x0000
R Timer_Event_Control_TEC0XCTL0 0x0000000B 0x0000
R Timer_Event_Control_TEC0XCTL1 0x0000000B 0x0000
R Timer_Event_Control_TEC0XCTL2 0x0000000B 0x0000
R Timer_Event_Control_TEC0STA 0x0000000B 0x0000
R Timer_Event_Control_TEC0XINT 0x0000000B 0x0000
R Timer_Event_Control_TEC0IV 0x0000000B 0x0000
R UCS__Unified_System_Clock_UCSCTL0 0x0000000B 0x00F8
R UCS__Unified_System_Clock_UCSCTL1 0x0000000B 0x0060
R UCS__Unified_System_Clock_UCSCTL2 0x0000000B 0x11F3
R UCS__Unified_System_Clock_UCSCTL3 0x0000000B 0x0020
R UCS__Unified_System_Clock_UCSCTL4 0x0000000B 0x0404
R UCS__Unified_System_Clock_UCSCTL5 0x0000000B 0x0000
R UCS__Unified_System_Clock_UCSCTL6 0x0000000B 0xC1ED
R UCS__Unified_System_Clock_UCSCTL7 0x0000000B 0x0711
R UCS__Unified_System_Clock_UCSCTL8 0x0000000B 0x0706
R USCI_A0__UART_Mode_UCA0CTLW0 0x0000000B 0x0081
R USCI_A0__UART_Mode_UCA0CTL0 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0CTL1 0x0000000D 0x81
R USCI_A0__UART_Mode_UCA0BRW 0x0000000B 0x001A
R USCI_A0__UART_Mode_UCA0BR0 0x0000000D 0x1A
R USCI_A0__UART_Mode_UCA0BR1 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0MCTL 0x0000000D 0x11
R USCI_A0__UART_Mode_UCA0STAT 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0RXBUF 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0TXBUF 0x0000000D 0x1E
R USCI_A0__UART_Mode_UCA0ABCTL 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0IRCTL 0x0000000B 0x0000
R USCI_A0__UART_Mode_UCA0IRTCTL 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0IRRCTL 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0ICTL 0x0000000B 0x0200
R USCI_A0__UART_Mode_UCA0IE 0x0000000D 0x00
R USCI_A0__UART_Mode_UCA0IFG 0x0000000D 0x02
R USCI_A0__UART_Mode_UCA0IV 0x0000000B 0x0000
R USCI_A0__SPI_Mode_UCA0CTLW0__SPI 0x0000000B 0x0081
R USCI_A0__SPI_Mode_UCA0CTL0__SPI 0x0000000D 0x00
R USCI_A0__SPI_Mode_UCA0CTL1__SPI 0x0000000D 0x81
R USCI_A0__SPI_Mode_UCA0BRW__SPI 0x0000000B 0x001A
R USCI_A0__SPI_Mode_UCA0BR0__SPI 0x0000000D 0x1A
R USCI_A0__SPI_Mode_UCA0BR1__SPI 0x0000000D 0x00
R USCI_A0__SPI_Mode_UCA0MCTL__SPI 0x0000000D 0x11
R USCI_A0__SPI_Mode_UCA0STAT__SPI 0x0000000D 0x00
R USCI_A0__SPI_Mode_UCA0RXBUF__SPI 0x0000000D 0x00
R USCI_A0__SPI_Mode_UCA0TXBUF__SPI 0x0000000D 0x1E
R USCI_A0__SPI_Mode_UCA0ICTL__SPI 0x0000000B 0x0200
R USCI_A0__SPI_Mode_UCA0IE__SPI 0x0000000D 0x00
R USCI_A0__SPI_Mode_UCA0IFG__SPI 0x0000000D 0x02
R USCI_A0__SPI_Mode_UCA0IV__SPI 0x0000000B 0x0000
R USCI_B0__SPI_Mode_UCB0CTLW0__SPI 0x0000000B 0x0101
R USCI_B0__SPI_Mode_UCB0CTL0__SPI 0x0000000D 0x01
R USCI_B0__SPI_Mode_UCB0CTL1__SPI 0x0000000D 0x01
R USCI_B0__SPI_Mode_UCB0BRW__SPI 0x0000000B 0x0000
R USCI_B0__SPI_Mode_UCB0BR0__SPI 0x0000000D 0x00
R USCI_B0__SPI_Mode_UCB0BR1__SPI 0x0000000D 0x00
R USCI_B0__SPI_Mode_UCB0STAT__SPI 0x0000000D 0x00
R USCI_B0__SPI_Mode_UCB0RXBUF__SPI 0x0000000D 0x00
R USCI_B0__SPI_Mode_UCB0TXBUF__SPI 0x0000000D 0x00
R USCI_B0__SPI_Mode_UCB0ICTL__SPI 0x0000000B 0x0200
R USCI_B0__SPI_Mode_UCB0IE__SPI 0x0000000D 0x00
R USCI_B0__SPI_Mode_UCB0IFG__SPI 0x0000000D 0x02
R USCI_B0__SPI_Mode_UCB0IV__SPI 0x0000000B 0x0000
R USCI_B0__I2C_Mode_UCB0CTLW0 0x0000000B 0x0101
R USCI_B0__I2C_Mode_UCB0CTL0 0x0000000D 0x01
R USCI_B0__I2C_Mode_UCB0CTL1 0x0000000D 0x01
R USCI_B0__I2C_Mode_UCB0BRW 0x0000000B 0x0000
R USCI_B0__I2C_Mode_UCB0BR0 0x0000000D 0x00
R USCI_B0__I2C_Mode_UCB0BR1 0x0000000D 0x00
R USCI_B0__I2C_Mode_UCB0STAT 0x0000000D 0x00
R USCI_B0__I2C_Mode_UCB0RXBUF 0x0000000D 0x00
R USCI_B0__I2C_Mode_UCB0TXBUF 0x0000000D 0x00
R USCI_B0__I2C_Mode_UCB0I2COA 0x0000000B 0x0000
R USCI_B0__I2C_Mode_UCB0I2CSA 0x0000000B 0x0000
R USCI_B0__I2C_Mode_UCB0ICTL 0x0000000B 0x0200
R USCI_B0__I2C_Mode_UCB0IE 0x0000000D 0x00
R USCI_B0__I2C_Mode_UCB0IFG 0x0000000D 0x02
R USCI_B0__I2C_Mode_UCB0IV 0x0000000B 0x0000
R Watchdog_Timer_WDTCTL 0x0000000B 0x6980

Best regards,

Pawel

over 6 years ago

0 Caleb Overbay over 6 years ago

TI__Genius 15370 points

Hi Pawel,

The values in UCSCTL0 are automatically modified by the FLL so it's not very helpful to report the value. It would be more helpful if you provided the snippet of code that configures the UCS module as well as letting me know your system frequency, supply voltage, VCORE level, and values of any external crystals. Once I have this information it will be easier to help diagnose the issue.

Best regards,
Caleb Overbay

0 Pawel Mag over 6 years ago in reply to Caleb Overbay

Prodigy 20 points

Many thanks for the prompt reply.

Here is the snippet of code where UCS module is configured:

void init_SetVcoreUp (unsigned int level)
{
  // Open PMM registers for write
  PMMCTL0_H = PMMPW_H;
  // Set SVS/SVM high side new level
  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
  // Set SVM low side to new level
  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
  // Wait till SVM is settled
  while ((PMMIFG & SVSMLDLYIFG) == 0);
  // Clear already set flags
  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
  // Set VCore to new level
  PMMCTL0_L = PMMCOREV0 * level;
  // Wait till new level reached
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
  // Set SVS/SVM low side to new level
  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
  // Lock PMM registers for write access
  PMMCTL0_H = 0x00;
}

void init_Clock(void){
    init_SetVcoreUp (0x01);
    init_SetVcoreUp (0x02);                            // sec Vcore to lev 2 in order to support CPU speed up to 20Mhz
    UCSCTL3 = SELREF_2;                                // Set DCO FLL reference = REFO
    UCSCTL6 &= ~XT1OFF;                                // turn on xtal1
    UCSCTL6 |= XTS;									   // XTAL1 in HF mode.
    UCSCTL0 = 0x0000;                                  // Set lowest possible DCOx, MODx -- these will be automatically modified
    do{                                                // Loop until XT1, XT1 & DCO stabilizes
        UCSCTL7 &= ~(XT1HFOFFG | XT1LFOFFG | DCOFFG);    		   // Loop until XT1, XT1 & DCO stabilizes
        SFRIFG1 &= ~OFIFG;                             // Clear fault flags
    }
    while (SFRIFG1 & OFIFG);                           // Test oscillator fault flag
    UCSCTL4 = SELS__XT1CLK | SELA__DCOCLKDIV | SELM__DCOCLKDIV;  // XTAL1 clock for SMCLK, and for ACLK DCOCLKDIV
    __bis_SR_register(SCG0);                           // Disable the FLL control loop
    UCSCTL1 = DCORSEL_6;                               // Select DCO range to support 16MHz operation
    UCSCTL2 = FLLD_1 | DCO_MULTIPLIER;                 // Set DCO Multiplier for 16.384 MHz
                                                       // (N + 1) * FLLRef = Fdco
                                                       // (499 + 1) * 32768 = 16.384 MHz

    __bic_SR_register(SCG0);                           // Enable the FLL control loop
                                                       // Worst-case settling time for the DCO when the DCO range bits have been
                                                       // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
                                                       // UG for optimization.
                                                       // 32 x 32 x 8 MHz / 32,768 Hz ~ 250000 = MCLK cycles for DCO to settle
    __delay_cycles(1000000);
    //CCR0
    TA0CCTL0 = CCIE;                                   // CCR0 interrupt enabled
    TA0CTL   = TASSEL_1 + MC_1;                        // ACLK, up mode for TIMERA0
    TA0CCR0  = UPTIMVALUE_DCO;                         // set up threshold timer value
    UCSCTL8 &= ~ACLKREQEN;                             // turn OFF request for ACLK clock signal. Without this, TIMER would exit LMP mode in order to count

    SFRIE1 |= OFIE; //enable NMI interrupt handling (sys.c)
}

I am using external 4MHz crystal. MCU supply voltage is 3V. This initialization (init_Clock function) is executed only at first power-up sequence. In my application device works for 8 hours at main power supply and then 2 hours at battery supply. Switching between this two state is the moment where my application hangs in NMI interrupt. To turn off MCU in battery mode i am using macro:

 _BIS_SR(CPUOFF);								  // Turn off CPU

and to turn on in powered mode:

__bic_SR_register_on_exit(OSCOFF | SCG0 | SCG1);

In this NMI interrupt handler my application hangs and couldn't reset DCOFFG flag:

/**
 * This ISR is used to catch clock fault flags.
 */
__interrupt void UserNMIIsr(void)
{
    switch(__even_in_range(SYSUNIV, 0x08))
    {
    case 0x04: //OFIFG interrupt pending
        UCSCTL7 &= ~(XT1HFOFFG | XT1LFOFFG | DCOFFG);
        break;
    case 0x02: // NMIIFG interrupt pending (highest priority)
    case 0x06: // ACCVIFG interrupt pending
    case 0x08: // BUSIFG interrupt pending (Not present on all devices. See device-specific datasheet)
        break; // Do not care about those interrupts
    default:
        break;
    }
}

Regards,
Pawel

0 Caleb Overbay over 6 years ago in reply to Pawel Mag

TI__Genius 15370 points

Hi Pawel,

A few things I noticed:

The default XT1DRIVE settings in HF mode are for 24 to 32MHz. You should use XT1DRIVE_0 for the 4 to 8MHz range
When DCOFFG is set is means that DCO bits in UCSCTL0 are either 0 or 31. This could be caused by a lot of things but it's worth considering whether your DCORSEL settings are correct for 16MHz operation. Try adjusting the DCORSEL up or down and see the results.
When entering and exiting LPM's I recommend using the __bis_SR_register(LPM0_bits) and __bic_SR_register_on_exit(LPM0_bits) notation respectively so it's more apparent which operating modes you're using.
In you UNMI ISR you never clear the OFIFG in SFRIFG1. You need to clear this bit or your code will constantly enter the interrupt even if there is no fault present anymore.

Overall, it's concerning that the interrupt triggers when transitioning from main power to battery. This signals to me that the device is losing power or at least experiencing a dip on VCC. If the device is subjected to too significant of a dip and the PMM isn't setup correctly to handle such circumstances, the MCU may not be operating correctly. I would monitor VCC when the switch occurs and ensure you've setup the PMM correctly to handle when VCC dips below safe operating range for 16MHz operation.

Best regards,
Caleb Overbay

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MSP430F5171: Unified Clock System module problem