I am getting a XT1LFOFFG fault in UCSCTL7
At start I think I should get it because "After a PUC, the UCS module default configuration is:
• XT1 in LF mode is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK "
So I expect a fault,
So then I set ACLK to REFO with
UCS_initClockSignal(UCS_ACLK, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1 );
And Turn off XT1 with UCS_turnOffXT1();
So then I try to clear the flag:
if (UCSCTL7 & XT1LFOFFG) // If XTL LF Mode is set clear it, this is disabled
{
UCSCTL7 &= ~XT1LFOFFG; // clear it
}
And the XT1LFOFFG percists.
It says
XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set. XT1LFOFFG is set if a XT1 fault condition exists. XT1LFOFFG can be cleared by software. If the XT1 fault condition still remains, XT1LFOFFG is set. 0b = No fault condition occurred after the last reset. 1b = XT1 fault (LF mode). A XT1 fault occurred after the last reset. |
If it is off and ACLK is 32768 Hz from REFo
And SMCLK and MCLK are 7,372,800 Hz using the REFO as input to DCO FLL why is there a fault?
void CLK_Init(void) { uint16_t status; // I believe when everything is done the clocks are: // ACLK = 32768 Hz using REFO // MCLK = 7,372,800 Hz from REFO // SMCLK = 7,372,800 Hz from REFO // Set DCO FLL reference = REFO // Any external Crystals are off _BIC_SR(SCG0); // Make sure the FLL is turned on. UCS_initClockSignal(UCS_FLLREF, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1 ); // Set ACLK = REFO UCS_initClockSignal(UCS_ACLK, UCS_REFOCLK_SELECT, UCS_CLOCK_DIVIDER_1 ); UCS_initClockSignal(UCS_SMCLK, UCS_DCOCLKDIV_SELECT, UCS_CLOCK_DIVIDER_1 ); // Set Ratio and Desired MCLK Frequency and initialize DCO UCS_initFLLSettle(7373, // kHz 225 ); // 7372.8/32.768 = 225 // In this mode we are below 8 MHz so we can have PMMCOREV0 = 1.8V // so now that the frequency is lower we can set the voltage. status = PMM_setVCore(PMM_CORE_LEVEL_0); if (status == STATUS_FAIL) while(1); // we have problems. When debugging stop here. //PMM_enableSvsHSvmH(); // in this mode we have highside so turn on. //PMM_enableSvsLSvmL(); // we need low side enabled in this mode. //PMM_enableSvsLReset(); // We should never see a low voltage event UCS_turnOffXT1(); // Make sure external 32.768 kHz Crystal is off if (UCSCTL7 & XT1LFOFFG) // If XTL LF Mode is set clear it, this is disabled { UCSCTL7 &= ~XT1LFOFFG; // clear it } UCS_turnOffXT2(); // Make sure external 14.7456 MHz Crystal is off //Verify if the Clock settings are as expected clockValue[0] = UCS_getMCLK(); clockValue[1] = UCS_getSMCLK(); clockValue[2] = UCS_getACLK(); T1Enable_Port(); if (d.Debug[7]) print_clock_values(); return; }