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Original question:

MSP430FR5972: LPM4.5

MSP430FR5972: When does an ISR get called when exiting LPM4.5 on MSP430FR2433

lloyd konneker
Expert 1790 points
Part Number: MSP430FR5972

I understand that exiting LPM4.5 invokes the boot loader and then the reset vector.  That RAM and registers are lost, including the stack pointer, which the reset handler should set up.  But I don't understand when the ISR for an interrupt is invoked, if at all, when the interrupt wakes from LPM4.5.  Usually an interrupt pushes the SP and PC onto the stack, and the RTI instruction return from interrupt pops them.  Since the registers and RAM are lost, where would the PC and SP be pushed and popped?  And normally (on other mcu's ?) the ISR clears an interrupt flag. Sorry if I am mixing concepts that don't apply to the MSP430FR.

Maybe just refer me to a document.

In my application, I just want an event on a GPIO port (from an Abracon RTC) to wake from LPM4.5.

For example, I am trying to understand the code in this thread:  e2e.ti.com/.../623293

  • 0
    Guru 96825 points
    According to SLAU367O sec. 1.4.3.3, the interrupt only occurs if/when the interrupt is re-enabled after the restart.

    As a slight twist: example program msp430fr6x7x_lpm4-5_02.c [slac686e] never re-enables on a restart, and so has no ISR at all (don't push the button too quick, I guess (:-))).
  • 0 in reply to Bruce McKenney
    Expert 1790 points
    Thanks, I should read more carefully. Its extraordinary.

    Not needing the ISR is useful. I want to use run-to-completion tasks, which always run as ISR's or dispatched from an ISR. The only interrupt is the RTC which is marking time til the next scheduled task. If it's a wake from lpm4.5, I'll just call the scheduled task (which must schedule another task) before entering lpm4.5 again.
  • 0 in reply to Bruce McKenney
    Expert 1790 points
    I finally realize what you mean by "don't push the button too quick." It means there is a race. The interrupt could come after enabling the interrupt and before entering LPM4.5. In that case, since there is no ISR defined by the example code, something bad happens (it depends on what the toolchain is defaulting for the interrupt vectors?) So the example is not production ready. You can't omit the ISR unless you are sure the interrupt cannot come until after you enter LPM.

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