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MSP430FR5972: WATCHDOG TIMEOUT

Part Number: MSP430FR5972

Hi,

I am configuring the watchdog timer  as  WDTCTL =WDTPW +  WDTCNTCL+ WDTSSEL_0 + WDTIS_1.Which is working perfectly but sometimes when watchdog expires and then I check reboot reason it shows me reset reason as LPM wakeup not watchdog timeout in Reset vector generator.

Can you tell what could be the reason for this?

  • Hi,

    Thanks for your post. Did you use LPM3.5 or LPM4.5 in your software?

    B.R.

    Winter Yu

  • May I confirm with you if you adopt LPM3.5 in you system?
  • I am using LPM4.5.And these are the setting which  I am using for LPM4.5 wakeup.

    /* Configure P1.6 as an Interrupt*/

    /*P1.6 hi/low edge*/
    P1IES |= BIT6;

    /*Clear all P1 interrupt flags*/
    P1IFG = RESET_TO_ZERO;

    /*P1.6 interrupt enabled*/
    P1IE |= BIT6;

    /*Disable watchdog before entering into LPM*/
    STOP_WDT

    /*Disable the GPIO power-on default high-impedance mode to activate*/
    PM5CTL0 &= ~LOCKLPM5;

    /*Open PMM Registers for write*/
    PMMCTL0_H = PMMPW_H;
    PMMCTL0_L |= PMMREGOFF;

    /*Disable high-side SVS*/
    PMMCTL0_L &= ~(SVSHE);

    /*Lock PMM Registers*/
    PMMCTL0_H = RESET_TO_ZERO;

    /* Enter LPM4 Note that this operation does not return. The LPM will exit through a RESET event, resulting in a re-start*/
    __bis_SR_register(LPM4_bits);

    /*MCU will wait here until the interrupt receive on P1.6*/
    while (1)
    {

    }

  • I am using LPM4.5.And these are the setting which  I am using for LPM4.5 wakeup.

    /* Configure P1.6 as an Interrupt*/

    /*P1.6 hi/low edge*/
    P1IES |= BIT6;

    /*Clear all P1 interrupt flags*/
    P1IFG = RESET_TO_ZERO;

    /*P1.6 interrupt enabled*/
    P1IE |= BIT6;

    /*Disable watchdog before entering into LPM*/
    STOP_WDT

    /*Disable the GPIO power-on default high-impedance mode to activate*/
    PM5CTL0 &= ~LOCKLPM5;

    /*Open PMM Registers for write*/
    PMMCTL0_H = PMMPW_H;
    PMMCTL0_L |= PMMREGOFF;

    /*Disable high-side SVS*/
    PMMCTL0_L &= ~(SVSHE);

    /*Lock PMM Registers*/
    PMMCTL0_H = RESET_TO_ZERO;

    /* Enter LPM4 Note that this operation does not return. The LPM will exit through a RESET event, resulting in a re-start*/
    __bis_SR_register(LPM4_bits);

    /*MCU will wait here until the interrupt receive on P1.6*/
    while (1)
    {

    }

  • Hi,

    The LPM4.5 will also cause a MCU BOR reboot and the reset cause store at SYSRSTIV as WDT reset as well.  

    Best Regards,

    If my post helped solve your issue, please click on the  VERIFY ANSWER    button. 

    Winter,

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