i'm wondering when the FOUR ISR are triggered:
USCIAB0TX_VECTOR
USCIAB0RX_VECTOR
USCIAB1TX_VECTOR
USCIAB1RX_VECTOR
Couldn't find any Information about that.
Kindly help
Thank you.
Regards,
Sameer Batra
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i'm wondering when the FOUR ISR are triggered:
USCIAB0TX_VECTOR
USCIAB0RX_VECTOR
USCIAB1TX_VECTOR
USCIAB1RX_VECTOR
Couldn't find any Information about that.
Kindly help
Thank you.
Regards,
Sameer Batra
There is one interrupt vector to handle the TX events of two USCI modules (A and B), and one interrupt vector to handle the RX events of two modules; see section 19.3.16 of the User's Guide.
The F47177 has four USCI modules (A0/B0/A1/B1), so it needs four vectors. The gcc header file says:
#define USCIAB1TX_VECTOR (19) /* 0xFFE4 USCI A1/B1 Transmit */ #define USCIAB1RX_VECTOR (20) /* 0xFFE6 USCI A1/B1 Receive */ ... #define USCIAB0TX_VECTOR (25) /* 0xFFF0 USCI A0/B0 Transmit */ #define USCIAB0RX_VECTOR (26) /* 0xFFF2 USCI A0/B0 Receive */
Dear Clemens,
Thanks for your quick response .
As u said the following :
The F4777 has four USCI modules (A0/B0/A1/B1), so it needs four vectors. The gcc header file says:
#define USCIAB1TX_VECTOR (19) /* 0xFFE4 USCI A1/B1 Transmit */ #define USCIAB1RX_VECTOR (20) /* 0xFFE6 USCI A1/B1 Receive */ ... #define USCIAB0TX_VECTOR (25) /* 0xFFF0 USCI A0/B0 Transmit */ #define USCIAB0RX_VECTOR (26) /* 0xFFF2 USCI A0/B0 Receive */
Section 21.3.7 of the User's Manual says:
USCI_Ax and USCI_Bx share the same interrupt vectors. In I2C mode the state change interrupt flags UCSTTIFG, UCSTPIFG, UCNACKIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax are routed to one interrupt vector. The I2C transmit and receive interrupt flags UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax share another interrupt vector.
(See page 21-25.)
The I²C state change interrupts go the same vector that handles Ax Receive.
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