MSP430 Team,
I am confused on errata USCI35. From slaz546p:
These timings from the device datasheet slas897A are:
Question 1: Why does the errata only indicate standard mode? Doesn't this errata also impact fast mode? I don't see any control bits for the peripheral that select between these two modes. Rather, the only difference I see is in the tHD,STA and tSU,STA timings above, and the timings are much tighter above 100 kHz.
Question 2: The tHD_STA and tSU,STA timings shown in datasheet section 5.34 above appear to be requirements when the MSP430 is in I2C slave mode. We don't say anything about what the actual timings will be when the MSP430 is in master mode. So the errata seems to be saying that the MSP430 can violate its own setup and hold timings. We do not know if it is violating the actual timing requirements for other slaves. Correct?
Thank you,
David