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MSP430F5244: USCI35 errata on I2C repeated start timings

Part Number: MSP430F5244

MSP430 Team,

I am confused on errata USCI35.  From slaz546p:

These timings from the device datasheet slas897A are:

Question 1: Why does the errata only indicate standard mode?  Doesn't this errata also impact fast mode?  I don't see any control bits for the peripheral that select between these two modes.  Rather, the only difference I see is in the tHD,STA and tSU,STA timings above, and the timings are much tighter above 100 kHz.

Question 2: The tHD_STA and tSU,STA timings shown in datasheet section 5.34 above appear to be requirements when the MSP430 is in I2C slave mode.  We don't say anything about what the actual timings will be when the MSP430 is in master mode.  So the errata seems to be saying that the MSP430 can violate its own setup and hold timings.  We do not know if it is violating the actual timing requirements for other slaves.  Correct?

Thank you,

David

  • Hello David,

    Hopefully I can help clear things up for you.

    David M. Alter said:
    Question 1: Why does the errata only indicate standard mode?  Doesn't this errata also impact fast mode?  I don't see any control bits for the peripheral that select between these two modes.  Rather, the only difference I see is in the tHD,STA and tSU,STA timings above, and the timings are much tighter above 100 kHz.

    The errata only indicates standard mode because that's the only mode that's affected. The reason you don't see any mode control bits for the peripheral is due to the I2C spec. When the fSCL frequency is greater than 100kHz, then the module knows the mode is Fast mode. When it's equal to or less than 100kHz, the module knows it's in Standard mode. Thus, the SCL clock frequency defines the mode. From an implementation perspective, it wouldn't make sense to add an additional bit to indicate what mode you want when the SCL frequency already defines that and could be configured manually for a different mode - there could be a conflict. Make sense?

    Fast Mode

    David M. Alter said:
    Question 2: The tHD_STA and tSU,STA timings shown in datasheet section 5.34 above appear to be requirements when the MSP430 is in I2C slave mode.  We don't say anything about what the actual timings will be when the MSP430 is in master mode.  So the errata seems to be saying that the MSP430 can violate its own setup and hold timings.  We do not know if it is violating the actual timing requirements for other slaves.  Correct?

    Actually, these setup and hold times are for master mode because the master sends the repeated start condition to indicate that more data is coming across the bus without giving up control to perhaps another master device on the bus. Actually, the hold time shown in Section 5.34 above applies to both the normal START condition and for a repeated START condition (hence the parenthesis around the word "repeated"). Make sense?

    Repeated Start Condition

    Solutions to Common eUSCI and USCI Serial Communication Issues on MSP430™ MCUs

    Regards,

    James

    MSP Customer Applications

  • James Evans said:
    The errata only indicates standard mode because that's the only mode that's affected. The reason you don't see any mode control bits for the peripheral is due to the I2C spec. When the fSCL frequency is greater than 100kHz, then the module knows the mode is Fast mode. When it's equal to or less than 100kHz, the module knows it's in Standard mode. Thus, the SCL clock frequency defines the mode.

    After some digging, the USCI module may not be that smart. The setup and hold times could depend on a number of clock counts scaled across SCL frequencies. Thus, I suspect that this scaling doesn't cover all types of modes, which is the reason for this errata. Again, that's just my assumption.

    To be clear, this errata does not affect Fast mode operation. I'm assuming that SCL frequencies above 100kHz up to 400kHz are classified as Fast mode, but I would recommend configuring the SCL frequency to run at 200kHz or 400kHz to deliberately get away from the 100kHz point.

    I'll submit a bug adding a note explicitly stating that Fast mode is not affected.

    Regards,

    James

    MSP Customer Applications

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