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MSP430G2221: bug in USI configured as SPI master

Part Number: MSP430G2221

Hi,

there seems to be a bug in the HW when the USI is configured as SPI master. The following code configures the USI for 16-bit SPI master operation.

Then the code transfers 2x 16-bits on the SPI. However the FIRST transfer generates 17 clocks instead of the expected 16. All subsequent transfers correctly generate 16 clocks.

I consider this a HW issue, or did I miss a configuration step?


// configure SPI machine
   USICTL0 = USISWRST | USIOE | USIMST | USIPE5 | USIPE6 | USIPE7;     
   USICTL1 = USICKPH;
   USICKCTL = USISSEL_2;
   USICNT = USI16B;

// take it out of reset
   USICTL0 &= ~USISWRST;
   
// transfer FIRST 16 bits.
// THIS WILL GENERATE 17 CLOCK on SCLK. THIS IS WRONG (in my opinion)
   USICNT |= 16;
// wait thill transfer is complete
   while((USICTL1 & USIIFG) == 0);
// transfer SECOND 16 bits
// This transfer works as expected, generating 16 SCLK.
   USICNT |= 16;