MSP430F6745: I have a question about how to use COMP_B.

Thank you for answering.

We use COMP_B on mass-produced devices, but the delay time is less than 100 μs.

Since voltage reference is used when COMP_B is turned ON, it refers to tSETTLE in p60 of the data sheet.

Regards,
da

Thank you reply.

In the current program, a delay time of about 83 us is provided when COMP_B is initialized.
It does not meet the maximum delay time when COMP_B of the data sheet permits.

As a solution method without problems, it is an update of firmware, but it can not be done
because there are many targeted numbers.
It is necessary to conclude that the problem does not occur even with the current delay time.

We are considering the following.

Compare the conditions of use of the current device with the conditions (temperature and voltage trend etc.)
of 100 μs, and explain that no problem occurs.

We will refer to tSETTLE (75us) in the manual, so we will explain that this does not
occur as it is fully satisfied.

Regards,
Da

Hi Da,

I will not be able to give you a definite answer without having more details on your application.

The main things are:

- How do you use the Comparator in the application? How crucial is the proper function of it?

- What would happen in case the Comparator is not giving the correct result (in case it is not yet enabled) ? Do you include checks for wrong results? Or otherwise would this remain unnoticed?

I need to emphasize that I can only guarantee the value provided in the datasheet, which is 100 us. As you've assumed before the decision to update the value from 50 us to 100 us was based on behavior that we've tested in the low temperature range. Nonetheless, the datasheet value of 100 us enable time is what we specify and guarantee as maximum enable  time.

With regards to your question:

da said:

They are looking for information to judge whether coping is necessary.

this I cannot judge without details on the implementation, as indicated in the above questions.

In case this is not information that shall be shared openly in the forum I suggest the best way will be to work with the TI Sales team and take this thread offline.

Please let me know what is your preferred way to further get down to the solution.

Thanks and best regards,

Britta

I will organize the contents.

Since COMP_B uses the internal reference now, it makes code that gives a delay time of 75 μs or more.
tEN of COMP_B changes from 50 μs to 100 μs and the timing of tEN can not be satisfied.
Therefore, problems may occur.

Verify that the current code will cause this problem.
The code using COMP_B at low power is as follows.

    　　CBCTL1 |= CBON;                      ・・・bis.w #0x400,&CBCTL1  (D0B2 0400 08C2)
　　　asm("NOP");                                ・・・nop                   (4303)
　　　asm("NOP");                                ・・・nop                   (4303)
　　　asm("NOP");                                ・・・nop                   (4303)
　　　rd_cbout = (CBCTL1 & CBOUT);・・・mov.w &CBCTL1,R15     (421F 08C2)

Since it is using low power, the internal REFO is used as the clock.

Since three NOP instructions are used since turning ON COMP_B,
the delay is the shortest 88.5 us, so it is less than 100 us.

However, the instruction to read the register of COMP_B is a 2 cycle instruction.
It is thought that reading the register actually is 118 us increased by one cycle.

In the case of this instruction sequence, is it possible to think that interpretation
of the number of cycles to read is four cycles after turning ON?

If possible, it will be helpful if you also tell us the voltage and temperature conditions
of the device to be 100 μs. (When the temperature is low, it approaches 100 μs etc.)

Regards,
Da

Hi Britta,

Currently COMP_B is used to compare the internal reference and the external input.
In low power mode, comparison is done with REFO with the following code.

           source                                            disassembly                      Memory image

　　　CBCTL1 |= CBON;                         bis.w #0x400,&CBCTL1   (D0B2 0400 08C2)    3 cycle
　　　asm("NOP");                                   nop                                   (4303)                        1 cycle
　　　asm("NOP");                                   nop                                   (4303)
　　　asm("NOP");                                   nop                                   (4303)
　　　rd_cbout = (CBCTL1 & CBOUT);   mov.w &CBCTL1,R15      (421F 08C2)              2 cycle

Since three NOP instructions are used since turning ON COMP_B,
the delay is the shortest 88.5 us, so it is less than 100 us.

However, the instruction to read the register of COMP_B is a 2 cycle instruction.
If the reading timing is the second half of the instruction, one cycle is added as the delay time.
When 1 cycle is added, it becomes 117.9 us, so it is 100 μs or more of tEN_CMP.

In the case of this instruction sequence, is it possible to think that interpretation of the
number of cycles to read is four cycles after turning ON?

If possible, it will be helpful if you also tell us the voltage and temperature conditions of
the device to be 100 μs. (When the temperature is low, it approaches 100 μs etc.)

Regards,
Da