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MSP430F6745: I have a question about how to use COMP_B.

Expert 2780 points
Part Number: MSP430F6745

Hello,

I have a question about the following parameters of MSP430F6745.
"tEN_CMP" "Comparator enable time"

 Q1

The maximum value of the old data sheet (slas768D) is 50μs, and in the new data sheet (slas768E) it has been changed to 100μs, 
why was it changed?

Q2

When turning on COMP_B, there are times when it waits for tSETTLE or more, but is tSETTLE related?

Previous thread
e2e.ti.com/.../660629

Regards,
Da

  • Hi Da,

    Q1: Do you see any constraints with the enable time of 100us for your application?
    Q2: I don't see any tSETTLE in the datasheet, where have you found this spec?

    Best regards
    Lukas
  • Hi Da,

    thanks for your questions.
    Q1: This was updated based on findings during tests.
    Q2: With tSETTLE you're referring to the settling time of the voltage reference, correct? The settling time will have an impact on the Comparator if you use the shared reference for the Comparator. Please section 32.2.6 of the User's Guide for details.

    Please let me know if this helps or if you have more questions (especially on my understanding of your Q2).
    Best regards,
    Britta
  • Thank you for answering.

    We use COMP_B on mass-produced devices, but the delay time is less than 100 μs.

    Since voltage reference is used when COMP_B is turned ON, it refers to tSETTLE in p60 of the data sheet.

    Regards,
    da

  • Thank you for answering.

    In the new datasheet, the maximum value has been changed from 50 us to 100 μs. Do you know the condition to be the maximum value?
    In the previous thread, there was a reply that the stabilization time would be long at low temperature.

    Thank you for answering.

    tSETTLE is a parameter of the voltage reference.

    Extension of the delay time when COMP_B of the MSP 430 mass-produced program is turned ON is a problem.
    The sample program of COMP_B of MSP 430ware has a delay time of 75 μs. (Comment in program: // delay for the reference to settle)
    A program is created with reference to this program.
    If it is this delay time, I want to know the frequency with which problems of COMP_B operation occur.


    Regards,
    Da
  • Hi Da,

    unfortunately I don't know the conditions under which the maximum value could occur. As the datasheet is binding, this includes all devices we produce and sell, which then include variances (where 100us is the maximum).

    I'm sorry but I'm not sure I understand your other question. The 75us settling time is also written in the device datasheet, as you indicated in your thread before. I understand you use code snippets from MSP430Ware which is just fine. Could you explain what your last question is about?

    Thanks and best regards,
    Britta
  • Thank you reply.

    In the current program, a delay time of about 83 us is provided when COMP_B is initialized.
    It does not meet the maximum delay time when COMP_B of the data sheet permits.

    As a solution method without problems, it is an update of firmware, but it can not be done
    because there are many targeted numbers.
    It is necessary to conclude that the problem does not occur even with the current delay time.

    We are considering the following.

    Compare the conditions of use of the current device with the conditions (temperature and voltage trend etc.)
    of 100 μs, and explain that no problem occurs.

    We will refer to tSETTLE (75us) in the manual, so we will explain that this does not
    occur as it is fully satisfied.

    Regards,
    Da

  • Hi Da,

    I'm not sure I fully understood your remaining question.
    Can you explain to me what remains unclear on your side or where you'd need further assistance?

    Thanks and best regards,
    Britta
  • Hi Britta

    Recently, the data sheet has been updated (SLAS768D -> SLAS768E).
    Therefore, the value of tEN_COMP has been changed from 50μs to 100μs.
    Customers had been programmed to meet the old tEN_COMP value.
    With this change, there is a possibility that problems may occur in the result of COMP_B.

    They are looking for information to judge whether coping is necessary.
    They want to know to what extent the problem occurs in the result,
    and on what condition the problem occurs in the result.

    Currently COMP_B is delayed as follows.
    The content of COMP_B is acquired four cycles later?

    CBCTL1 |= CBON; bis.w #0x400,&CBCTL1 (D0B2 0400 08C2)
    asm("NOP"); nop (4303)
    asm("NOP"); nop (4303)
    asm("NOP"); nop (4303)
    rd_cbout = (CBCTL1 & CBOUT); mov.w &CBCTL1,R15 (421F 08C2)


    Best Regards,
    Da
  • Hi Da,

    I will not be able to give you a definite answer without having more details on your application.

    The main things are:

    - How do you use the Comparator in the application? How crucial is the proper function of it?

    - What would happen in case the Comparator is not giving the correct result (in case it is not yet enabled) ? Do you include checks for wrong results? Or otherwise would this remain unnoticed?

    I need to emphasize that I can only guarantee the value provided in the datasheet, which is 100 us. As you've assumed before the decision to update the value from 50 us to 100 us was based on behavior that we've tested in the low temperature range. Nonetheless, the datasheet value of 100 us enable time is what we specify and guarantee as maximum enable  time.

    With regards to your question:

    da said:
    They are looking for information to judge whether coping is necessary.

    this I cannot judge without details on the implementation, as indicated in the above questions.

    In case this is not information that shall be shared openly in the forum I suggest the best way will be to work with the TI Sales team and take this thread offline.

    Please let me know what is your preferred way to further get down to the solution.

    Thanks and best regards,

    Britta

  • I will organize the contents.

    Since COMP_B uses the internal reference now, it makes code that gives a delay time of 75 μs or more.
    tEN of COMP_B changes from 50 μs to 100 μs and the timing of tEN can not be satisfied.
    Therefore, problems may occur.

    Verify that the current code will cause this problem.
    The code using COMP_B at low power is as follows.

          CBCTL1 |= CBON;                      ・・・bis.w #0x400,&CBCTL1  (D0B2 0400 08C2)
       asm("NOP");                                ・・・nop                   (4303)
       asm("NOP");                                ・・・nop                   (4303)
       asm("NOP");                                ・・・nop                   (4303)
       rd_cbout = (CBCTL1 & CBOUT);・・・mov.w &CBCTL1,R15     (421F 08C2)

    Since it is using low power, the internal REFO is used as the clock.

    Since three NOP instructions are used since turning ON COMP_B,
    the delay is the shortest 88.5 us, so it is less than 100 us.

    However, the instruction to read the register of COMP_B is a 2 cycle instruction.
    It is thought that reading the register actually is 118 us increased by one cycle.

    In the case of this instruction sequence, is it possible to think that interpretation
    of the number of cycles to read is four cycles after turning ON?

    If possible, it will be helpful if you also tell us the voltage and temperature conditions
    of the device to be 100 μs. (When the temperature is low, it approaches 100 μs etc.)

    Regards,
    Da

  • Hi Britta,

    Currently COMP_B is used to compare the internal reference and the external input.
    In low power mode, comparison is done with REFO with the following code.

               source                                            disassembly                      Memory image

       CBCTL1 |= CBON;                         bis.w #0x400,&CBCTL1   (D0B2 0400 08C2)    3 cycle
       asm("NOP");                                   nop                                   (4303)                        1 cycle
       asm("NOP");                                   nop                                   (4303)
       asm("NOP");                                   nop                                   (4303)
       rd_cbout = (CBCTL1 & CBOUT);   mov.w &CBCTL1,R15      (421F 08C2)              2 cycle

    Since three NOP instructions are used since turning ON COMP_B,
    the delay is the shortest 88.5 us, so it is less than 100 us.

    However, the instruction to read the register of COMP_B is a 2 cycle instruction.
    If the reading timing is the second half of the instruction, one cycle is added as the delay time.
    When 1 cycle is added, it becomes 117.9 us, so it is 100 μs or more of tEN_CMP.

    In the case of this instruction sequence, is it possible to think that interpretation of the
    number of cycles to read is four cycles after turning ON?

    If possible, it will be helpful if you also tell us the voltage and temperature conditions of
    the device to be 100 μs. (When the temperature is low, it approaches 100 μs etc.)

    Regards,
    Da

  • Hi da,

    thanks a lot for the detailed description, this really helped me.
    My advice is to rather go for one additional NOP to add more time between the COPM_B ON and COMP_B READ. I understand that the calculation you've shown above calculates a delay time of 117.9 us which should be save. As the MSP430 includes a Pipeline CPU though it's hard to be sure when exactly the Bit set operation and Bit read operation will happen, as other instructions could be fetched in the meantime. Thus I'd recommend to increase the delay time, for example by one more NOP, to be on the safe side in case our application allows.

    Please let me know if this is an option for you.
    I'm sorry to say that I cannot disclose the conditions under which Comp_B t_EN is 100us as our test and characterization data is confidential.

    Best regards,
    Britta
  • Hi da,

    please note that I am going to close this thread as the main question is answered.
    We can still follow up other pending questions via the offline channel if needed.

    Best regards,
    Britta