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MSP432P401R: DAC Converter

Part Number: MSP432P401R

Hi,

I am working on MSP432P401R and DAC161S055EVM. As per some given guidlines here by senior memebers, I am able to set up SPI communication between MSP432 and DAC161s055. As given Timing diagram in script, I am getting perfect waveforms but I am facing a very strange issue at this moments.

According to DAC161 data sheet (page 7)  and MSp technical reference manual (page 940), waveforms of MOSI and SOMI should have shape (symmetry) when CS and CLK are runing and I have attached the reference image below from data sheet of DAC.

My problem is that , In my case when I was checking the waveforms for SCLK, CS, MOSI and SIMO. In the presence of SCLK (if I am attaching measurement probe to CLK pin), MOSI and SOMI waveforms are not symmetrical any more. MOSI has perfect diagram but SOMI has different shape and then DAC output remain at zero (idle position).

But when I do not measure the SCLK then the SOMI and MOSI have symmetrical shape and DAC analog output updates also as according to given digital input. (How I observed this CLK issue ,just accidently removed SCLK probe and I figured out this observation ).

I think, I have problem somewhere with the clock frequency of SPI protocol because I am providing SMCLK to SPI configuration protocol and it has 24 MHZ but bit clock generator of SPI can have maximum 20M Hz frequncy.
As per given SPI protocol information(block diagram 935 and page939 ) , bit clock frequency can be calculated but I am not understanding where should I apply this bit clock frequency and how pre divder will have impact to reduce SMCLK frequency.

Please help me out from this issue.

Many thanks for your kind help and for every sugesstion.

  • Hi Hasan,

    i assume that this issue comes from the load of the oscilloscope probe you add on the signal line.
    This load makes the signal slower and as you are running on a quite high speed with the SPI protocol this can delay the clock compared to the data signal in that way that it does not get the data correct anymore.

    So you can either try:
    - reducing the SPI clock speed
    - adding probe also to the MOSI signal
    - increasing the drive strength of the SPI signals, check this function: GPIO_setDriveStrengthHigh

    Note: looks like your measurement results have not been attached.

    Regards,
    Stefan
  • Hi Stefan,

    As always, You are my helper and savior :)

    I tried probe on SCLK and now it is working fine and getting required result. Thank you very much.
  • I have one more question. As I was giving one specific known data on the input of Dac just to make sure that it is working fine or not. Now, dac is working fine.

    I want to give input to dac from the output of adc.

    I have two questions regarding this:

    1 ) As per given data sheet information for both Adc and dac, they are having Vref 2.5 v and 4.096 v respectively. So here i need to rescale my output value because i can give input only 2.5 v maximum and ouput should be 2.5 v on dac analog output. (Make me correct , if it is wrong) . I am not getting how to scale this and how it will be written in c code. I think there will be decrement factor involved in rescaling because it should be one to one relation between analog input and analog output.Can you please tell me the mathematical calculation to rescale my Adc and dac scale ??

    2 ) As dac output data is being saved in uint_fast16_t buffer and dac input is also in the form of 3 buffer registers (need 3 bytes as per p 7 of dac data sheet).

    How should i read first adc output and write this to dac input ??

    Do you think , pointer can help me ??

    Many thanks for your time and answer.

  • Hi Hasan,

    i think i need to clarify a few typical nomenclatures first to get properly aligned.
    When working with a Microcontroller the typical view is out of the Microcontroller Eyes.
    This means in this case the ADC has an input and provides data, the DAC is on output (even if external) and need to get data.

    Yes, the DAC need to get 3 Bytes but it is 1 Command byte and then 2 Data bytes of the format uint_fast16_t . When handling this data i would also keep the split and just "merge" in the data send functions so that the 3 bytes get send out.

    The ADC of the MSP432 has 14 bits where as the DAC has 16 bits. With both having the same Reference Voltage of 2.5V
    So if you would like to keep the voltage range on both you need to scale the ADC value by a factor of (16-14)^2 = 2^2 = 4

    Regards,
    Stefan
  • Hi Stefan,

    I did not get your last point regarding scaling, sorry. If ADC will be scaled by the factor of 4 then adc value will be decreased more. A little more explanation please or mention me where I can find that basic information.

    The way , I was trying to calculate it is little different. For example ADC range [0 to 2.5 v] and DAC [0 to 4.096 v] and I want to make same scale for both so DAC vales would be multiplied with this [(2.5/4) =0.625 ] factor but I think this way is also wrong.

  • Hi Hasan,

    some ADC basic:
    input value of ADC = analog input signal / Reference Voltage * ADC resolution
    so in your case (ADC has a resolution of 14 Bit)
    input value of ADC = analog input signal / 2.5V * 2^14
    -> ADC input signal can be a max of Reference Voltage.
    -> ADC max value can also just be ADC resolution which is 2^14 = 16384

    If you would like to have the input signal measured also set to the output on the DAC (thid DAC has a resolution of 16Bit) you need to scale the 14 of the ADC to the 16Bit of the DAC because if you put 16384 as a value to the DAC you only get
    16384/2^16 * 2.5 = 0.625 which is 1/4 of the max value

    Regards,
    Stefan

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