MSP430F6726: FLL specification

Section 5.2.8 of the User's Guide says:

The modulator mixes two DCO frequencies, f_DCO and f_DCO+1 to produce an intermediate effective frequency between f_DCO and f_DCO+1 […] The modulator mixes f_DCO and f_DCO+1 for 32 DCOCLK clock cycles and is configured with the MOD bits. When MOD = {0}, the modulator is off.

The modulator mixing formula is:

t = (32 – MOD) × t_DCO + MOD × t_DCO+1

So when looking at the average frequency, one MOD step is one 32th of one DCO step.

Section 5.2.7 says:

The FLL continuously counts up or down a frequency integrator. The output of the frequency integrator that drives the DCO can be read in UCSCTL0, UCSCTL1 (bits MOD and DCO). The count is adjusted +1 with the frequency f_FLLREFCLK/n (n = 1, 2, 4, 8, 12, or 16) or –1 with the frequency f_DCOCLK/[D × (N+1)].

So the cycle is different for correcting up or down.
For example, when you tell the FLL that you want the DCOCLK frequency to be 31 times the FLLREFCLK frequency, then the FLL counts the number of DCOCLK cycles that happen between two consecutive FLLREFCLK cycles. If the counter is lower than 31 at the next FLLREFCLK cycle, then the DCO runs too slow, and the FLL corrects up. If the counter exceeds 31 (which happens before the next FLLREFCLK cycle), then the DCO runs too fast, and the FLL corrects down.

Hi Cruijff,

1. All MOD bits are modified automatically during FLL operation. So you don't have to care the MOD 1 bit fluctuation range.
2. About the cycle of the FLL correction operation, it depends on your correction code, and you can toggle a IO to test it.

Best regards,
Stanford