CCS/MSP430FR2355: Measured Time Period for a Timer Delay doesn't match the Expected Value

Hi Yaman,

Bruce has already offered a great post, but please let me add more details.

Firstly, according to MSP430FR235x, MSP430FR215x Mixed-Signal Microcontrollers datasheet, you can easily find that VLO is not accurate enough for your application. It is strongly recommended to use XT1 oscillator crystal instead, since it is much more accurate and also low-power at the same time.

Secondly, in the MSP430FR4xx and MSP430FR2xx Family User's Guide, you can find the detailed description of TBCLR. You can see that setting TBCLR clears TBxR, so it is unnecessary to write TB0R = 0.

Last but not least, a friendly advice just for your reference: rather than using a DMM, maybe you can also consider another approach by using one oscilloscope. Configure one oscilloscope channel to be triggered by a falling edge with "Single" mode. Upon timer interrupt, you can toggle one MSP430 GPIO, and with oscilloscope you can capture that event easily and accurately. Certainly with this approach error still exists, and in order to minimize the error, you can leave the SELMS to the default option SELMS__DCOCLKDIV. Given the condition of LPM3, it is unnecessary to set SELMS to SELMS__VLOCLK because MCLK and SMCLK are off under LPM3.

I have modified you code to serve as an example for your reference. Hope it helps!

#include <msp430.h>

void main(void) {
    WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
    PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
    // to activate previously configured port settings

    P1OUT = 0x00;
    P2OUT = 0x00;
    P3OUT = 0x00;
    P4OUT = 0x00;
    P5OUT = 0x00;
    P6OUT = 0x00;

    P1DIR = 0xff;
    P2DIR = 0xff;
    P3DIR = 0xff;
    P4DIR = 0xff;
    P5DIR = 0xff;
    P6DIR = 0xff;

    P2SEL1 |= BIT6 | BIT7;                  // P2.6~P2.7: crystal pins
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);      // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag

    CSCTL4 = SELA__XT1CLK | SELMS__DCOCLKDIV;

    //Set timer
    TB0CCTL0 |= CCIE;                   // TBCCR0 interrupt enabled

    P1OUT |= BIT0;                              // Used as indicator

    TB0CCR0 = (32768 / 4) * 1 - 1;              // 1s
    TB0CTL = TBCLR;                             // Clear Timer
    TB0CTL = ID__4 | TBSSEL__ACLK | MC__UP;     // Input divider /4, ACLK, UP mode
    P1OUT ^= BIT0;                              // Indicating timer start
    __bis_SR_register(LPM3_bits | GIE);         // Enter LPM3 w/ interrupt
    __no_operation();                           // For debug use

    TB0CCR0 = (32768 / 4) * 2 - 1;              // 2s
    TB0CTL = TBCLR;                             // Clear Timer
    TB0CTL = ID__4 | TBSSEL__ACLK | MC__UP;     // Input divider /4, ACLK, UP mode
    P1OUT ^= BIT0;                              // Indicating timer start
    __bis_SR_register(LPM3_bits | GIE);         // Enter LPM3 w/ interrupt
    __no_operation();                           // For debug use

    TB0CCR0 = (32768 / 4) * 3 - 1;              // 3s
    TB0CTL = TBCLR;                             // Clear Timer
    TB0CTL = ID__4 | TBSSEL__ACLK | MC__UP;     // Input divider /4, ACLK, UP mode
    P1OUT ^= BIT0;                              // Indicating timer start
    __bis_SR_register(LPM3_bits | GIE);         // Enter LPM3 w/ interrupt
    __no_operation();                           // For debug use

    TB0CCR0 = (32768 / 4) * 4 - 1;              // 4s
    TB0CTL = TBCLR;                             // Clear Timer
    TB0CTL = ID__4 | TBSSEL__ACLK | MC__UP;     // Input divider /4, ACLK, UP mode
    P1OUT ^= BIT0;                              // Indicating timer start
    __bis_SR_register(LPM3_bits | GIE);         // Enter LPM3 w/ interrupt
    __no_operation();                           // For debug use

    TB0CCR0 = (32768 / 4) * 5 - 1;              // 5s
    TB0CTL = TBCLR;                             // Clear Timer
    TB0CTL = ID__4 | TBSSEL__ACLK | MC__UP;     // Input divider /4, ACLK, UP mode
    P1OUT ^= BIT0;                              // Indicating timer start
    __bis_SR_register(LPM3_bits | GIE);         // Enter LPM3 w/ interrupt
    __no_operation();                           // For debug use

    while(1){
        LPM4;
    }
}

#pragma vector = TIMER0_B0_VECTOR
__interrupt void TB0_ISR(void) {
    P1OUT ^= BIT0;   // Indicating interrupt
    __bic_SR_register_on_exit(LPM3_bits | GIE);
}

1s waveform attached below for your reference.

Hi Yaman,

With all due respect, I would like to challenge the results taken by DMM. Usually for DMM it's a trade-off between sample speed and resolution. For a typical 6.5-digit DMM, the true resolution at the fastest sample rate usually would be only 3.5-digit at most. In addition, the DMM is usually meant to be used for static measurements, and the sample rate is usually as slow as possible to achieve the best accuracy. As for our signal, which is actually a very fast pulse from P1.0, the DMM is very likely to be not responsive enough. Of course you can refer to the documents of your DMM for details, but generally in this case the results taken by DMM are reasonably unreliable.

It is strongly recommended to use a better approach rather than the DMM. I can understand your situation where an oscilloscope is unfortunately unavailable (still strongly recommended to get one as soon as possible), and I can offer you one more simple solution: using a MSP430. Only one GPIO and one timer are required. Utilize the interrupt of that GPIO to start or stop the timer. Actually you can use any microcontroller to do it, but as for MSP430 I have created the code below to serve as an example for your reference. When using it, simply connect the P1.0 and GND of both MSP430.

#include <msp430.h>
#define NUMBER_OF_TESTS 5

unsigned char i;
unsigned short int CountVal[NUMBER_OF_TESTS];

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop watchdog timer
    // Disable the GPIO power-on default high-impedance mode
    // to activate previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    P2SEL1 |= BIT6 | BIT7;                  // P2.6~P2.7: crystal pins
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);      // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag

    CSCTL4 = SELA__XT1CLK | SELMS__DCOCLKDIV;

    P1OUT |= BIT0;                          // Configure P1.0 as pulled-up
    P1REN |= BIT0;                          // P1.0 pull-up register enable
    P1IES |= BIT0;                          // P1.0 interrupt on falling edge
    P1IFG = 0;                              // P1.0 IFG cleared
    P1IE |= BIT0;                           // P1.0 interrupt enabled

    for(i = 0; i < NUMBER_OF_TESTS; i++){
        __bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/interrupt
        __no_operation();                   // For debug
    }

    while(1){
        LPM4;
    }
}

// Port 1 interrupt service routine
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void){
    if(P1IES & BIT0){
        // On falling edge
        TB0CTL = ID__4 | TBSSEL__ACLK | MC__CONTINUOUS; // Input divider /4, ACLK, Continuous mode
        P1IES &= ~BIT0;         // P1.0 interrupt on rising edge
    }
    else{
        // On rising edge
        TB0CTL &= ~MC;          // Stops the timer
        CountVal[i] = TB0R;     // Record timer count value
        TB0CTL = TBCLR;         // Clear Timer
        P1IES |= BIT0;          // P1.0 interrupt on falling edge
        __bic_SR_register_on_exit(LPM0_bits | GIE);
    }
    P1IFG &= ~BIT0;             // P1.0 IFG cleared
}

Correct results attached below for your reference. Hope this one helps!

By the way, regarding this question:

Yaman Sangar said:

When I use the debug mode, however, I see that once TB0R reaches the value set by the CCR0 register, it stays there and doesn't count further. I would expect it to roll back and still keep counting, at least while the ISR is being executed because the MC bits get cleared only after exiting the ISR. Would I be correct in thinking that's how it will work?

According to MSP430FR4xx and MSP430FR2xx Family User's Guide, the timer count changes at the rising edge of Timer Clock.

Keep in mind that Timer Clock is 32768Hz, while the CPU clock (MCLK) is 1MHz by default. In this case, Timer Clock is relatively very slow, and the program relatively executes so fast that the timer seems to be not operating at all. If MCLK is not that fast (e.g. when both are 32768Hz by CSCTL4 = SELA__XT1CLK | SELMS__XT1CLK), then you can easily observe the change of timer count.

However, keep in mind that P1.0 is used as the indicator so that the CPU clock (MCLK) should be as fast as possible to minimize the measurement error (which is interval between the time of timer interrupt and the time of P1.0 going high). In this case, please keep the SELMS to the default option SELMS__DCOCLKDIV.