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MSP430F5329: About the current increase after returning from the UCS fail-safe state

Part Number: MSP430F5329


I have question about of UCS Module Fail-Safe Operation.
We are facing the issue of increased power consumption due to UCS fail-safe operation.
We are using XT1 operation ins LF mode, when a clock failure occurs in XT1, the fail-safe function switches the clock source, and as a result only MSP430 has a current increase of about 4μA.

Although the oscillator failure has been removed and the DCOFFG, XT1LFOFFG, and OFIFG registers have been checked to confirm that the failure has been removed, a current increase of about 1μA can be seen compared to before the occurrence of the oscillator failure.

We predicted that the current consumption would be equal since the clock resources would return to their pre-fault state when the MSP430 recovers from the oscillator failure. Wwhat is the reason for the 1A current increase?

Best Regards,

  • Hi H.U,

    When the clock source switch from XT1 to REFO due to the XT1 fail, the REFO ON causes the 4uA current increase. It's clear.

    But if the XT1 is back and all the error flags are cleared, the clock source switches back to the XT1. The current should be no difference to the pre-fault state, would you please share your test case if possible? thanks.

    Best regards,
    Jovi He
  • Hello H.U.,
    have you been able to resolve the problem? Is there still anything we could do for you on this topic?

    Best regards
  • Hi Peter,

    Sorry for the late reply.

    This problem is actually occurring on my customer's board. Therefore, I am asking the customer about the details of the test.
    I'll get back to you as soon as I have get that information.

    Best Regards.
  • Hi,

    This problem seems to be due to the DCO modulator.

    After recovering from an oscillator failure, it has been found that once the DCO modulator is disabled(DISMOD = 1) and then enabled(DISMOD = 0) again, the current consumption is restored. This behavior has been reproduced on multiple customer boards.

    Why does the fail-safe feature increase the current consumption of the DCO modulator?

    Best Regards,

  • H.U,

    wich power consumption values do you compare LPM3 vs. LPM3 or AM vs. AM?

    Also which clock source is used for which clock this would help to better understand whats going on here.

    Actually I see no reasoning why the fail safe clock switching for the LFXT1 should influence the DCO modulation bit.

  • Hi,

    I checked the design implemenation and can confirm DISMOD bit of register UCSCTL1 is only reset with a PUC. The reset value is ZERO.

    So an OFIFG event can never set the DISMOD to logical 1 to disable the modulation with an OFIFG event. This leads me to the assumption that someting in the code is wrong.

    I strongly recommend to check all accesses to UCSCTL1!

  • Hi Dietmar,

    They are experimentally disabling DCO in their software in order to investigate the phenomenon of increased current consumption after recovery from oscillator failure.
    It is clear that the failsafe function is not operating DISIMOD.

    The current consumption after recovery from oscillator failure is increased, but once the DCO is disabled by software and enabled again, the increased 1 uA disappears.

    From the results obtained in this experiment, we think that the fail-safe operation may change some settings of the DCO modulator.

    Best Regards,

  • HU,

    I mean if you had faults on the LFXT1 and you got the fault interrupt it means you had noise on XT1 crystal.
    In this case the corresponding NMI should handle these events and clear the fails but also handle the faults with respect to the FLL.
    If the FLL was using the LFXT1 from crystal as reference clock via ACLK I stronlgy recommend to reinit the FLL as well ensuring and regulates back to LFXT1 and not hanging in strange regulation loops due to incorrect applied clocks during fault appearance.

    Hope this makes sense.