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MSP430F5335: DriverLib UCS_initFLL() stops

Part Number: MSP430F5335
Other Parts Discussed in Thread: MSP430WARE,

When power cycle the system, it boots up and runs fine.  If there is an error and I trigger POR `

PMMCTL0 |= PMMPW + PMMSWBOR;`, then the next time I try to  increase the micro controller rate, like so

PMM_setVCore(PMM_CORE_LEVEL_3);  // Increase Voltage
UCS_initFLLSettle(20000, 610);   // speed up uC

The WDT times out and the system gets stuck on the line `__bis_SR_register(SCG0);` in the `void UCS_initFLL(uint16_t fsystem, uint16_t ratio)` in driverlib. Why would it get stuck in that line?  Here is the listing of the file.  I only added step_id variable to track how far the code executed.

void UCS_initFLL(uint16_t fsystem, uint16_t ratio) {
    uint16_t d, dco_div_bits;
    uint16_t mode = 0;

    // Save actual state of FLL loop control, then disable it. This is needed to
    // prevent the FLL from acting as we are making fundamental modifications to
    // the clock setup.
    uint16_t srRegisterState = __get_SR_register() & SCG0;

    d = ratio;
    // Have at least a divider of 2
    dco_div_bits = FLLD__2;

    step_id = 7;

    if (fsystem > 16000) {
        d >>= 1;
        mode = 1;
    } else {
        // fsystem = fsystem * 2
        fsystem <<= 1;
    }

    step_id = 8;
    while (d > 512) {
        // Set next higher div level
        dco_div_bits = dco_div_bits + FLLD0;
        d >>= 1;
    }
    step_id = 9;

    // Disable FLL
    __bis_SR_register(SCG0);

    step_id = 10;
    // Set DCO to lowest Tap
    HWREG8(UCS_BASE + OFS_UCSCTL0_H) = 0x0000;

    step_id = 11;
    // Reset FN bits
    HWREG16(UCS_BASE + OFS_UCSCTL2) &= ~(0x03FF);
    step_id = 12;
    HWREG16(UCS_BASE + OFS_UCSCTL2) = dco_div_bits | (d - 1);

    step_id = 13;

    if (fsystem <= 630) {  // fsystem < 0.63MHz
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_0;
    } else if (fsystem < 1250) {  // 0.63MHz < fsystem < 1.25MHz
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_1;
    } else if (fsystem < 2500) {  // 1.25MHz < fsystem <  2.5MHz
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_2;
    } else if (fsystem < 5000) {  // 2.5MHz  < fsystem <    5MHz
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_3;
    } else if (fsystem < 10000) {  // 5MHz    < fsystem <   10MHz
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_4;
    } else if (fsystem < 20000) {  // 10MHz   < fsystem <   20MHz
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_5;
    } else if (fsystem < 40000) {  // 20MHz   < fsystem <   40MHz
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_6;
    } else {
        HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_7;
    }

    // Re-enable FLL
    __bic_SR_register(SCG0);

    while (HWREG8(UCS_BASE + OFS_UCSCTL7_L) & DCOFFG) {
        // Clear OSC flaut Flags
        HWREG8(UCS_BASE + OFS_UCSCTL7_L) &= ~(DCOFFG);

        // Clear OFIFG fault flag
        HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG;
    }

    // Restore previous SCG0
    __bis_SR_register(srRegisterState);

    if (mode == 1) {
        // fsystem > 16000
        // Select DCOCLK
        HWREG16(UCS_BASE + OFS_UCSCTL4) &= ~(SELM_7 + SELS_7);
        HWREG16(UCS_BASE + OFS_UCSCTL4) |= SELM__DCOCLK + SELS__DCOCLK;
    } else {
        // Select DCODIVCLK
        HWREG16(UCS_BASE + OFS_UCSCTL4) &= ~(SELM_7 + SELS_7);
        HWREG16(UCS_BASE + OFS_UCSCTL4) |= SELM__DCOCLKDIV + SELS__DCOCLKDIV;
    }
}

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