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MSP430F5329: Clock switching time by UCS fail‐safe operation

Part Number: MSP430F5329

Hi,

I have question about UCS fail-safe.
When the MCLK and ACLK source is sourced from XT1 and operating in LF mode, MCLK and ACLK is switched to REFO if an oscillator failure occurs.
How long does it take to switch to REFO after the XT1 supply stop?
Also, I think that the clock supplied to the CPU and peripheral modules is stopped during this period. Is my recognition correct?

Best Regards,
H.U