CCS/MSP-EXP432P4111: CCS/MSP-EXP432P4111 SPI Issue

I suggest you use 3-wire mode and wiggle CS (as a GPIO) yourself. That gives you full control over the delay.

Curiously enough, I don't see any examples for this mode, even though it's what I use for pretty much every SPI device ever.

I dug this out of my CCS archive. It talks to an ST LIS3DH via 3-wire+GPIO-CS. It doesn't do much, but it's small.

No warranty, and all that.

///
//      lis3dh-432.c
//      Poke at LIS3DH on Adafruit breakout board
//
#include "msp.h"
#include <stdint.h>
#define SPIU    EUSCI_B0
#define HZ      3000000UL       // more or less
#define SPI_HZ  1000000UL       // 1MHz clock

//  LIS3DH registers
#define WHO_AM_I    0x0F
#define CTRL_REG1   0x20
volatile uint8_t rreg;          // Register 0x20 should read as 0x06 since that's what we set
volatile uint8_t who_am_i;      // Register 0x0F should be 0x33 for the LIS3DH

#define CS_LO() do {P3->OUT &= ~BIT0;} while (0)
#define CS_HI() do {P3->OUT |=  BIT0;} while (0)

///
//  spi_init()
//  Set UCB0 to SPI, Master, 1MHz, mode=(1,1), 3-wire
//
void
spi_init(void)
{
    SPIU->CTLW0 = EUSCI_B_CTLW0_SWRST|
                  EUSCI_B_CTLW0_SSEL__SMCLK|EUSCI_B_CTLW0_SYNC|
                  EUSCI_B_CTLW0_MODE_0|EUSCI_B_CTLW0_MST|EUSCI_B_CTLW0_MSB|
                  (1*EUSCI_B_CTLW0_CKPL)|(0*EUSCI_B_CTLW0_CKPH); // mode=(1,1)
    SPIU->BRW = HZ/SPI_HZ;          // SPI clock rate
    SPIU->CTLW0 &= ~EUSCI_B_CTLW0_SWRST; // Out of reset
    P1->SEL0 |=  (BIT5|BIT6|BIT7);  // UCB0 per SLAS826G Table 6-62
    P1->SEL1 &= ~(BIT5|BIT6|BIT7);
    P3->OUT |= BIT0;                // P3.0 as /CS (but not STE)
    P3->DIR |= BIT0;
    return;
}

///
//  spix()
//  Exchange one byte
//
uint8_t
spix(uint8_t b)
{
    while (!(SPIU->IFG & EUSCI_B_IFG_TXIFG)) /*EMPTY*/;
    SPIU->TXBUF = b;
    while (!(SPIU->IFG & EUSCI_B_IFG_RXIFG)) /*EMPTY*/;
    b = SPIU->RXBUF;
    return(b);
}

///
//  lis_wrr()
//  Write LIS3DH register
//
void
lis_wrr(uint8_t reg, uint8_t val)
{
    CS_LO();
    (void)spix(0x00 | reg); // W bit
    (void)spix(val);
    CS_HI();
    return;
}

///
//  lis_rdr()
//  Read LIS3DH register
//
uint8_t
lis_rdr(uint8_t reg)
{
    uint8_t val;
    CS_LO();
    (void)spix(0x80 | reg); // R bit (no MS, I suppose)
    val = spix(0x55);
    CS_HI();
    return(val);
}

///
//  main()
//  Write LIS3DH CTRL_REG1 and read it back
//
void
main(void)
{
	WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD;		// stop watchdog timer
	P1->OUT &= ~BIT0;               // Launchpad LED P1.0
	P1->DIR |=  BIT0;
	spi_init();
	who_am_i = lis_rdr(WHO_AM_I);   // Register WHO_AM_I (0x0F) should read as 0x33
	while (1)
	{
	    P1->OUT ^= BIT0;
	    lis_wrr(CTRL_REG1, 0x06);   // CTRL_REG1 (0x20): Disable Xen
	    rreg = lis_rdr(CTRL_REG1);  // Read it back
	    __delay_cycles(HZ/3);       // 1/3 second
	}
}