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CCS/MSP430F6736: UART Receiver problem on EVM430F6736

Part Number: MSP430F6736
Other Parts Discussed in Thread: MSP430F6779, , MSP430F6749, MSP430F67491, MSP430F67791, MSP430F47197, MSP430F4794, MSP430AFE252, MSP430AFE253, MSP430AFE251

Tool/software: Code Composer Studio

Hi TI Team,

We have working with EVM430F6736 energy meter. In UART communication, Transmit the data to other device is working fine. but in receiver part, still not working. Receiver interrupt flag isn't enabling.

In which below mention our serial initialization, ( Baud rate = 115200 or 9600, 8bit data, mode = 1).


    /* We only need two modes for the serial characters in the work we have done to date.
       Just support those for the time being */
    if (mode == 0)
    {
        /* 7-bit character, even parity */
#if defined(__MSP430_HAS_UART0__)
        ctl0 = PENA | PEV | SWRST;
#else
        ctl0 = UC7BIT | UCPEN;
#endif
    }
    else
    {
        /* 8-bit character, no parity */
#if defined(__MSP430_HAS_UART0__)
        ctl0 = CHAR | SWRST;
#else
        ctl0 = 0;
#endif
    }
    /* Use ACLK for slow bit rates. Use SMCLK for higher bit rates */
    if (bit_rate <= 4800L)
    {
        bitrate_divider = (32768L*16L)/bit_rate;
#if defined(__MSP430_HAS_UART0__)
        ctl1 = SSEL0;               /* ACLK */
#else
        ctl1 = UCSSEL_1 | UCSWRST;  /* ACLK */
#endif
    }
    else
    {
#if defined(__MSP430F6736__)  ||  defined(__MSP430F6749__)  ||  defined(__MSP430F67491__)  ||  defined(__MSP430F6779__)  ||  defined(__MSP430F67791__)
        /* 24MHz clock */
        bitrate_divider = (32768L*768L*16L)/bit_rate;
#elif defined(__MSP430F4794__)  ||  defined(__MSP430F47197__)
        /* 16MHz clock */
        bitrate_divider = (32768L*512L*16L)/bit_rate;
#elif defined(__MSP430AFE251__)  ||  defined(__MSP430AFE252__)  ||  defined(__MSP430AFE253__)
        /* Exactly 8MHz clock */
        bitrate_divider = (8000000L*16L)/bit_rate;
#else
        /* 8MHz clock */
        bitrate_divider = (32768L*256L*16L)/bit_rate;
#endif
#if defined(__MSP430_HAS_UART0__)
        ctl1 = SSEL1;               /* SMCLK */
#else
        ctl1 = UCSSEL_2 | UCSWRST;  /* SMCLK */
#endif
    }
    bitrate_divider++;
#if defined(__MSP430_HAS_EUSCI_A0__)  ||  defined(__MSP430_HAS_UART0__)
    mctl = (bitrate_divider & 0x0E) >> 1;
    mctl = mod_patterns[mctl];
#else
    mctl = bitrate_divider & 0x0E;
#endif
    bitrate_divider >>= 4;
#if !defined(__MSP430_HAS_EUSCI_A0__)
    br1 = bitrate_divider >> 8;
    br0 = bitrate_divider;
#endif

    switch (port)
    {
#if defined(UART_0_SUPPORT)
    case 0:
    #if defined(__MSP430_HAS_USCI_AB0__)  ||  defined(__MSP430_HAS_USCI_A0__)  ||  defined(__MSP430_HAS_EUSCI_A0__)
        /* Configure the port with the reset bit held high */
        UCA0CTL1 |= UCSWRST;
        UCA0CTL0 = ctl0;
        UCA0CTL1 = ctl1;
        #if defined(__MSP430_HAS_EUSCI_A0__)
        UCA0BRW = bitrate_divider;
        UCA0MCTLW = ((uint16_t) mctl << 8);
        #else
        UCA0BR1 = br1;
        UCA0BR0 = br0;
        UCA0MCTL = mctl;
        UCA0STAT = 0;
        #endif
        UCA0TXBUF = 0;
        UCA0CTL1 &= ~UCSWRST;
        #if defined(UART_0_DMA_SUPPORT)
        //DMACTL0 |= (DMA1TSEL_3 | DMA2TSEL_4);
        #endif
        #if defined(__MSP430_HAS_USCI_AB0__)
        UC0IE |= UCA0RXIE;
        #else
        UCA0IE |= UCRXIE;
        #endif
    #elif defined(__MSP430_HAS_UART0__)
        UCTL0 = ctl0;
        UTCTL0 = ctl1;
        UBR10 = br1;
        UBR00 = br0;
        UMCTL0 = mctl;
        UCTL0 &= ~SWRST;
        /* Enable USART0 TXD/RXD */
        U0ME |= (UTXE0 | URXE0);
        U0IE |= URXIE0;
        /* If you do not initially kick the Tx port the TXEPT bit is not set. */
        TXBUF0 = 0;
    #endif
        return 0;

Kindly give any suggestion.

regards,

Anitha.L

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