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MSP430FR2033: Errata PMM32 Understanding point 3

Part Number: MSP430FR2033

Hi,

Can someone please help me clear up/ understand the wording at point three of PMM32 in errata rev U of MSP430FR2033.

Specifical MODCLK portion.

The following three events happen at the same time:
1) The device transitions from AM to LPM3/4 (e.g. during ISR exits or Status Register modifications),
AND
2) An interrupt is requested (e.g. GPIO interrupt),
AND
3) MODCLK is requested (e.g. triggered by ADC) or removed (e.g. end of ADC conversion).
Modules which can trigger MODCLK clock requests/removals are ADC and eUSCI.
If clock events are started by the CPU (e.g. eUSCI during SPI master transmission), they can’t occur at the same time as the power mode transition and thus should not be affected. The device should only be affected when the clock event is asynchronous to the power mode transition.

So if 1 and 3 occur at same time there shouldn't be a problem as will always be synchronous.

But for intance if a there was an SMclock or Aclk request at the same time as power mode transition then device would be affected?

as SMclock and ACLCK are independent to master clock and can occur Aysnchronously, refering to section 3.1 of technical reference manual?

  • So if 1 and 3 occur at same time there shouldn't be a problem as will always be synchronous. [YES, when referring to clock events started by the CPU.]

    But for instance if a there was an SMclock or Aclk request at the same time as power mode transition then device would be affected? [The errata condition #1 does not mention the SMCLK or ACLK clock sources for that condition, only MODCLK.  "Modules which can trigger MODCLK clock requests/removals...", so there shouldn't be a concern for those clock sources.]

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